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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-64751035c3bsm2094550a12.19.2025.11.27.10.23.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Nov 2025 10:23:37 -0800 (PST) Message-ID: <7f723f9c-93f4-43b2-8421-7af5f697c752@oss.qualcomm.com> Date: Thu, 27 Nov 2025 19:23:34 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/msm: Fix a7xx per pipe register programming To: Anna Maniscalco , Rob Clark , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org References: <20251127-gras_nc_mode_fix-v1-1-5c0cf616401f@gmail.com> <58570d98-f8f1-4e8c-8ae2-5f70a1ced67a@oss.qualcomm.com> <951138f1-d325-4764-a689-e1c3db12bb90@gmail.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <951138f1-d325-4764-a689-e1c3db12bb90@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: DZGYZRpAOVbW4XQm1nlgvHqv0crGJhVZ X-Proofpoint-ORIG-GUID: DZGYZRpAOVbW4XQm1nlgvHqv0crGJhVZ X-Authority-Analysis: v=2.4 cv=OPcqHCaB c=1 sm=1 tr=0 ts=6928972b cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=pGLkceISAAAA:8 a=6nOnMbRXApaOt5cKipAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI3MDEzOCBTYWx0ZWRfX585xNDyGA0Ae RhyQQOGhFIOXTeYjXxN1/NV0PJABlqs6xKHH/gemz39d7gOGon/Ii44oE5KNEEYp+Bh/2O5fg6Z QS+TXUcekl4wRmptTmf10SCkbK1+VUa+ISw0gNqeXBoijCBj1Jxn39RhsHEDcGGfmxMZb57dSbk prR3dYlAm3aprkIWwH2YLcKrpTd1Ef3Sac+MwFv8cIEsgb89TbXW7o9mscz9LGESWQltMjwSsuM DuOS2eL2xaNOHlxSfxuQzGCEfQxFxz1gXZ5G5B36i2f/hHSkaprndCyXHx8VxDJlBncD+KGa8RR w2ajGVcr4Ho9Q7wjvDNtyh/SMS6CLeP1TnezkYaR/w3ywQW3ToWBi1vrmnKyvHuxUHmRsUibSlW bkbvaY73ATmiOMhLEbNV323FdylpeQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 spamscore=0 malwarescore=0 phishscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511270138 On 11/27/25 7:14 PM, Anna Maniscalco wrote: > On 11/27/25 3:25 PM, Konrad Dybcio wrote: >> On 11/27/25 12:46 AM, Anna Maniscalco wrote: >>> GEN7_GRAS_NC_MODE_CNTL was only programmed for BR and not for BV pipe >>> but it needs to be programmed for both. >>> >>> Program both pipes in hw_init and introducea separate reglist for it in >>> order to add this register to the dynamic reglist which supports >>> restoring registers per pipe. >>> >>> Fixes: 91389b4e3263 ("drm/msm/a6xx: Add a pwrup_list field to a6xx_info") >>> Signed-off-by: Anna Maniscalco >>> --- >>>   drivers/gpu/drm/msm/adreno/a6xx_catalog.c |  9 ++- >>>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c     | 91 +++++++++++++++++++++++++++++-- >>>   drivers/gpu/drm/msm/adreno/a6xx_gpu.h     |  1 + >>>   drivers/gpu/drm/msm/adreno/adreno_gpu.h   | 13 +++++ >>>   4 files changed, 109 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> index 29107b362346..c8d0b1d59b68 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>> @@ -1376,7 +1376,6 @@ static const uint32_t a7xx_pwrup_reglist_regs[] = { >>>       REG_A6XX_UCHE_MODE_CNTL, >>>       REG_A6XX_RB_NC_MODE_CNTL, >>>       REG_A6XX_RB_CMP_DBG_ECO_CNTL, >>> -    REG_A7XX_GRAS_NC_MODE_CNTL, >>>       REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, >>>       REG_A6XX_UCHE_GBIF_GX_CONFIG, >>>       REG_A6XX_UCHE_CLIENT_PF, >>> @@ -1448,6 +1447,12 @@ static const u32 a750_ifpc_reglist_regs[] = { >>>     DECLARE_ADRENO_REGLIST_LIST(a750_ifpc_reglist); >>>   +static const struct adreno_reglist_pipe a750_reglist_pipe_regs[] = { >>> +    { REG_A7XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, >> At a glance at kgsl, all gen7 GPUs that support concurrent binning (i.e. >> not gen7_3_0/a710? and gen7_14_0/whatever that translates to) need this > > Right. > > I wonder if gen7_14_0 could be a702? No, a702 is a702 in kgsl Konrad > > If we do support one of those a7xx GPUs that don't have concurrent binning then I need to have a condition in hw_init for it when initializing REG_A7XX_GRAS_NC_MODE_CNTL > >> >> Konrad > > > Best regards,