From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5354C433DB for ; Wed, 10 Mar 2021 20:58:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8691164FCA for ; Wed, 10 Mar 2021 20:58:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230341AbhCJU5b (ORCPT ); Wed, 10 Mar 2021 15:57:31 -0500 Received: from z11.mailgun.us ([104.130.96.11]:36835 "EHLO z11.mailgun.us" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231231AbhCJU5D (ORCPT ); Wed, 10 Mar 2021 15:57:03 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1615409822; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: From: References: Cc: To: Subject: Sender; bh=5XWw8PFNwF6LFhiLkbPkKIEa4bbVxzhuAVG5qfayj/w=; b=dfnsUmiWWKlOgLzH6T9RiZ7P02WpPiYZZ+x5zu6f4f/re8HZRNr8hG2ch2g1rDDfvnupcCr1 beTSLHzJZOka5DTtSDCshc/q7JnS5xEkgCdGPEV7kn/I3x76HHSEAVy9jLjtqx5teypM1bet bOmeGPWadO7gySJ9yHAQjcMu42g= X-Mailgun-Sending-Ip: 104.130.96.11 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-west-2.postgun.com with SMTP id 6049329c155a7cd23434f6ea (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 10 Mar 2021 20:57:00 GMT Sender: hemantk=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 70F22C433C6; Wed, 10 Mar 2021 20:57:00 +0000 (UTC) Received: from [10.46.162.249] (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: hemantk) by smtp.codeaurora.org (Postfix) with ESMTPSA id C8164C433CA; Wed, 10 Mar 2021 20:56:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C8164C433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=hemantk@codeaurora.org Subject: Re: [PATCH v2 RESEND] bus: mhi: core: Wait for ready state after reset To: Jeffrey Hugo , manivannan.sadhasivam@linaro.org Cc: bbhatt@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <1615408918-7242-1-git-send-email-jhugo@codeaurora.org> From: Hemant Kumar Message-ID: <80b6c87a-001c-96ae-d0ce-f41b48362d80@codeaurora.org> Date: Wed, 10 Mar 2021 12:56:59 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <1615408918-7242-1-git-send-email-jhugo@codeaurora.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 3/10/21 12:41 PM, Jeffrey Hugo wrote: > After the device has signaled the end of reset by clearing the reset bit, > it will automatically reinit MHI and the internal device structures. Once > That is done, the device will signal it has entered the ready state. > > Signaling the ready state involves sending an interrupt (MSI) to the host > which might cause IOMMU faults if it occurs at the wrong time. > > If the controller is being powered down, and possibly removed, then the > reset flow would only wait for the end of reset. At which point, the host > and device would start a race. The host may complete its reset work, and > remove the interrupt handler, which would cause the interrupt to be > disabled in the IOMMU. If that occurs before the device signals the ready > state, then the IOMMU will fault since it blocked an interrupt. While > harmless, the fault would appear like a serious issue has occurred so let's > silence it by making sure the device hits the ready state before the host > completes its reset processing. > > Signed-off-by: Jeffrey Hugo Reviewed-by: Hemant Kumar -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project