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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7992d0e2ab3sm2772219b3a.64.2025.10.10.05.08.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Oct 2025 05:08:23 -0700 (PDT) Message-ID: <81ac4acb-3e0a-4e4c-a5b9-bcc5a949b8c9@oss.qualcomm.com> Date: Fri, 10 Oct 2025 20:08:18 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur To: Konrad Dybcio , Kamal Wadhwa , Dmitry Baryshkov Cc: Krzysztof Kozlowski , Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-14-24b601bbecc0@oss.qualcomm.com> <20251008073123.GA20592@hu-kamalw-hyd.qualcomm.com> <6bf19804-7ce2-4cb6-bdbd-dc12c18330df@oss.qualcomm.com> From: "Aiqun(Maria) Yu" Content-Language: en-US In-Reply-To: <6bf19804-7ce2-4cb6-bdbd-dc12c18330df@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: xveiCqawsCH-2nwCfqHccVn4Dgq0y2ao X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA5MDA5OCBTYWx0ZWRfX45JNvnSvKIAj jQdL4BfGCpKva74HC9iYLD+86GWTyKFH8GrQ/G2oNwZ4SaXOAWnbtSFVnQV3m2ZJ9n80QOMVigX rKqyCLB9URavq3/q98FFhS9czDsR7OEiJlNr+T6ZKtUkGtB3ri+CE+3GANkgCDb0Q3MwwUnWCfl SGpc80NO7mLZkRshLF59OIHsYt+hNiI0qbys3ufMDLnG1mJC7mLb6MGJ9loKXsLp32apSO80GAi YzcjjkKiYoSCZ/6ydTyE7G+E4ZEotSEct20Ys5q+BtFTOdX0OX74jD3KBiY1Hznm5TF/+fBANaz w3AQ2nPNXn7MdH92llpdyTghxRQ1Y5RG4eOWj9s4nH4jfuHNFLWx9Ev7Sx2xmTvfTdnnwntD+s0 Z+rEnRFzCFgwFU5e7QqYdKx1A7DK3w== X-Authority-Analysis: v=2.4 cv=DISCIiNb c=1 sm=1 tr=0 ts=68e8f73a cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=fbgB7Lw66JwkRMScquwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: xveiCqawsCH-2nwCfqHccVn4Dgq0y2ao X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-10_02,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 phishscore=0 impostorscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510090098 On 10/8/2025 5:15 PM, Konrad Dybcio wrote: > On 10/8/25 9:31 AM, Kamal Wadhwa wrote: >> Hi Krzysztof, Dmitry, Konrad, >> >> On Thu, Sep 25, 2025 at 09:57:02PM +0300, Dmitry Baryshkov wrote: >>> On Thu, Sep 25, 2025 at 10:34:52PM +0900, Krzysztof Kozlowski wrote: >>>> On Thu, 25 Sept 2025 at 22:14, Dmitry Baryshkov >>>> wrote: >>>>> >>>>> On Thu, Sep 25, 2025 at 05:08:54PM +0900, Krzysztof Kozlowski wrote: >>>>>> On Thu, 25 Sept 2025 at 15:34, Pankaj Patil >>>>>> wrote: >>>>>>> >>>>>>> From: Kamal Wadhwa >>>>>>> >>>>>>> Add multiple instance of PMH0110 DT node, one for each assigned >>>>>>> SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur >>>>>>> CRD. >>>>>>> >>>>>>> Take care to avoid compilation issue with the existing nodes by >>>>>>> gaurding each PMH0110 nodes with `#ifdef` for its corresponding >>>>>>> SID macro. So that only the nodes which have the their SID macro >>>>>>> defined are the only ones picked for compilation. >>>>>>> >>>>>>> Signed-off-by: Kamal Wadhwa >>>>>>> Signed-off-by: Pankaj Patil >>>>>>> --- >>>>>>> arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++- >>>>>>> 1 file changed, 65 insertions(+), 1 deletion(-) >>>>>>> >>>>>>> diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi >>>>>>> index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644 >>>>>>> --- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi >>>>>>> +++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi >>>>>>> @@ -7,6 +7,8 @@ >>>>>>> #include >>>>>>> >>>>>>> &spmi_bus0 { >>>>>>> + >>>>>>> +#ifdef PMH0110_D_E0_SID >>>>>> >>>>>> NAK >>>>>> >>>>>> I already explained on IRC in great details why. >>>>> >>>>> A short summary or a link to a channel / date would be nice in order to >>>>> include other people into the discussion. >>>>> >>>> >>>> Of course but: >>>> 1. You were there so maybe you remember the arguments, and: >>>> 2. I'm offline, using phone, not having laptop, replying during my >>>> personal time off just before merge window so any emergency time >>>> should be spent on important matters instead these two huge patch >>>> bombs adding such usage I already said: NO, don't do this. >>> >>> >>> Well, If I'm asking, it means I don't rememebr the discussion. And I >>> defeinitely didn't know that you are spending your personal vacation >>> time in ML. And if the discussion was with some other people, then >>> somebody else can drop the response to the question. >> >> Just wanted to give some background on this patch. >> Even though PMH0104 and PMH0110 are common (b/w Kaanapali and Glymur), >> they don't share the SIDs. So we tried to use status="disabled" to handle >> this but we observed that because of the node name being common in the >> two included files, it ends up overwriting the previous node with the >> same name. >> >> eg- >> #include "pmh0104.dtsi" // assume contains pmic@4 { ...}; >> #include "pmh0110.dtsi" // assume contains pmic@4 { status=disabled;}; >> >> Here intention was to use the pmh0104 on sid-4, but it gets overwritten >> with the pmh0110 on sid-4 ( with status disabled). This is why we ended >> up using the `#ifdef`, ensuring that we can control the exact pmic that >> gets picked by using the PMXXX_SID macro. >> >> side note, i did `grep` in the `/arch/arm64/boot/dts/` and i see a lot >> of instances of `#if...` present in that. Assuming the concern here is >> about the use of `#ifdef`. >> >> Can you suggest some alternative approach? >> or comment on below approaches:- >> >> 1. Can I use `pmic@pm0104_d_e0` ? >> This may work but looks like a departure from the current format >> i.e `pmic@` used in the arch/arm64/boot/dts/qcom. >> >> 2. Create PMIC-ID based pmic dts? `pmh0104_d_e0.dtsi` and likewise add all >> pmics? But this could mean creating too many pmic files and end up >> bloating the dts/qcom/ directory. >> >> 3. Add the nodes directly inside glymur-pmics.dtsi ( not using #include)? > > This is what we did for x1e after similar conundrums > > It adds up to the maintenance cost in theory, but the alternative was worse It seems a common scenario for different targets! Considering that a PMIC chip can be reused across different targets—and even within a single platform multiple instances of the same PMIC may exist—it might be beneficial to define separate common DTSI files for each allocated SID." When the device tree is another language to interpret the hardware, shall we change the sentence more easily structured? For example, kaanapali actually have 4*PMH0110 mounted with SPMI0, and each PMH0110 have different SID(3, 5, 6, 8) allocated like(pseudocode, not tested, just for better understanding the ideas): #define PMH0110_D_E0_SID 3 #include "pmh0110_spmi0".dtsi #define PMH0110_F_E0_SID 5 #include "pmh0110_spmi0".dtsi #define PMH0110_G_E0_SID 6 #include "pmh0110_spmi0".dtsi #define PMH0110_I_E0_SID 8 #include "pmh0110_spmi0".dtsi Glymur actually have 3*PMH0110 mounted 2 with SPMI0,, and the other one with SPMI1, and each PMH0110 have different SID allocated(pseudocode, not tested, just for better understanding the ideas): #define PMH0110_SPMI0 0x1 #include "pmh0110_spmi0".dtsi #define PMH0110_SPMI0 0x7 #include "pmh0110_spmi0".dtsi #define PMH0110_SPMI1 0x5 #define "pmh0110_spmi1".dtsi Request a brainstorming here. Welcome the ideas! > > Konrad -- Thx and BRs, Aiqun(Maria) Yu