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[83.9.31.20]) by smtp.gmail.com with ESMTPSA id oy17-20020a170907105100b0087bd50f6986sm8898136ejb.42.2023.02.01.10.27.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Feb 2023 10:27:20 -0800 (PST) Message-ID: <8212dd18-50db-8e83-23ff-2155b19611e0@linaro.org> Date: Wed, 1 Feb 2023 19:27:19 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.0 Subject: Re: [PATCH v2 2/2] clk: qcom: gpucc-sdm845: fix clk_dis_wait being programmed for CX GDSC Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org References: <20230201172305.993146-1-dmitry.baryshkov@linaro.org> <20230201172305.993146-2-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20230201172305.993146-2-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 1.02.2023 18:23, Dmitry Baryshkov wrote: > The gdsc_init() function will rewrite the CLK_DIS_WAIT field while > registering the GDSC (writing the value 0x2 by default). This will > override the setting done in the driver's probe function. > > Set cx_gdsc.clk_dis_wait_val to 8 to follow the intention of the probe > function. > > Fixes: 453361cdd757 ("clk: qcom: Add graphics clock controller driver for SDM845") > Reviewed-by: Stephen Boyd > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Konrad > > Changes since v1: > - Fixed the _val suffix in .clk_dis_wait_val. > > --- > drivers/clk/qcom/gpucc-sdm845.c | 7 +------ > 1 file changed, 1 insertion(+), 6 deletions(-) > > diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c > index 110b54401bc6..970d7414bdf0 100644 > --- a/drivers/clk/qcom/gpucc-sdm845.c > +++ b/drivers/clk/qcom/gpucc-sdm845.c > @@ -22,8 +22,6 @@ > #define CX_GMU_CBCR_SLEEP_SHIFT 4 > #define CX_GMU_CBCR_WAKE_MASK 0xf > #define CX_GMU_CBCR_WAKE_SHIFT 8 > -#define CLK_DIS_WAIT_SHIFT 12 > -#define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT) > > enum { > P_BI_TCXO, > @@ -121,6 +119,7 @@ static struct clk_branch gpu_cc_cxo_clk = { > static struct gdsc gpu_cx_gdsc = { > .gdscr = 0x106c, > .gds_hw_ctrl = 0x1540, > + .clk_dis_wait_val = 0x8, > .pd = { > .name = "gpu_cx_gdsc", > }, > @@ -193,10 +192,6 @@ static int gpu_cc_sdm845_probe(struct platform_device *pdev) > value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT; > regmap_update_bits(regmap, 0x1098, mask, value); > > - /* Configure clk_dis_wait for gpu_cx_gdsc */ > - regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK, > - 8 << CLK_DIS_WAIT_SHIFT); > - > return qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap); > } >