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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa50b28fe55sm456496666b.4.2024.11.25.04.50.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Nov 2024 04:51:00 -0800 (PST) Message-ID: <833280a4-7014-45e9-852e-3384fe9d5cd4@oss.qualcomm.com> Date: Mon, 25 Nov 2024 13:50:59 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 To: Yuanjie Yang , Krzysztof Kozlowski , ulf.hansson@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bhupesh.sharma@linaro.org, andersson@kernel.org, konradybcio@kernel.org Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_tingweiz@quicinc.com, quic_zhgao@quicinc.com References: <20241122065101.1918470-1-quic_yuanjiey@quicinc.com> <20241122065101.1918470-2-quic_yuanjiey@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: D55Fu-j5TzUC5klR5b6R-lo_eIVDc6_A X-Proofpoint-ORIG-GUID: D55Fu-j5TzUC5klR5b6R-lo_eIVDc6_A X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 impostorscore=0 priorityscore=1501 suspectscore=0 phishscore=0 spamscore=0 bulkscore=0 mlxlogscore=826 adultscore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411250108 On 25.11.2024 3:20 AM, Yuanjie Yang wrote: > On Fri, Nov 22, 2024 at 01:35:28PM +0100, Krzysztof Kozlowski wrote: >> On 22/11/2024 09:40, Yuanjie Yang wrote: >>> On Fri, Nov 22, 2024 at 08:04:31AM +0100, Krzysztof Kozlowski wrote: >>>> On 22/11/2024 07:51, Yuanjie Yang wrote: >>>>> Add SDHC1 and SDHC2 support to the QCS615 Ride platform. >>>>> >>>>> Signed-off-by: Yuanjie Yang >>>>> --- [...] >>>>> + bus-width = <8>; >>>>> + qcom,dll-config = <0x000f642c>; >>>>> + qcom,ddr-config = <0x80040868>; >>>>> + supports-cqe; >>>>> + dma-coherent; >>>>> + mmc-ddr-1_8v; >>>>> + mmc-hs200-1_8v; >>>>> + mmc-hs400-1_8v; >>>>> + mmc-hs400-enhanced-strobe; >>>> >>>> These are properties of memory, not SoC. If the node is disabled, means >>>> memory is not attached to the SoC, right? >>>> >>>>> + status = "disabled"; >>> Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc, >>> they are memory configurations that need to be written to the ioaddr. >>> And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config, >>> they indicate the bus speed at which the host contoller can operate. >>> If the node is disabled, which means Soc don't support these properties. >> No, that is not the meaning of node is disabled. When node is disabled, >> it means board does not have attached memory. >> >> Move the memory related properties to the board. > > Thanks, Ok I understand, I will move the memory related > properties(qcom,dll-config and qcom,ddr-config) to the > board dts in next version. DDR/DLL tuning seem to be done per SoC and not per board. Konrad