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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9e56643609sm101287266b.155.2024.10.31.13.39.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Oct 2024 13:39:08 -0700 (PDT) Message-ID: <8355dc9f-ec3b-4738-b4e1-41351af2fa91@oss.qualcomm.com> Date: Thu, 31 Oct 2024 21:39:06 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/4] arm64: dts: qcom: sar2130p: add support for SAR2130P To: Dmitry Baryshkov , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Krishna Kurapati , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241030-sar2130p-dt-v2-0-027364ca0e86@linaro.org> <20241030-sar2130p-dt-v2-3-027364ca0e86@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241030-sar2130p-dt-v2-3-027364ca0e86@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: 6oDsYAYB49Ysp3xl0ONLH6h_MTTitAIc X-Proofpoint-GUID: 6oDsYAYB49Ysp3xl0ONLH6h_MTTitAIc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 malwarescore=0 bulkscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410310156 On 30.10.2024 12:50 PM, Dmitry Baryshkov wrote: > Add DT file for the Qualcomm SAR2130P platform. > > Co-developed-by: Konrad Dybcio > Signed-off-by: Konrad Dybcio > Signed-off-by: Dmitry Baryshkov > --- > arch/arm64/boot/dts/qcom/sar2130p.dtsi | 3091 ++++++++++++++++++++++++++++++++ > 1 file changed, 3091 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi > new file mode 100644 > index 0000000000000000000000000000000000000000..d4f5514cbdaf2d0a1c1cd367be2d7a08246d203e > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi > @@ -0,0 +1,3091 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2024, Linaro Limited > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen { }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <19200000>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32000>; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { Krzysztof recently turned these lowercase, please follow suit [...] > + /* secdata region can be reused by apps */ This comment isn't very useful > + smem: smem@80900000 { > + compatible = "qcom,smem"; > + reg = <0x0 0x80900000 0x0 0x200000>; > + hwlocks = <&tcsr_mutex 3>; > + no-map; > + }; > + > + cpucp_fw_mem: cpucp-fw-region@80b00000 { Not sure if we want -region everywhere. Krzysztof? [...] > + soc: soc@0 { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > + compatible = "simple-bus"; Compatible first, please [...] > + #size-cells = <2>; > + ranges; > + status = "disabled"; A newline before status would be very cool [...] > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,sar2130p-pdc", "qcom,pdc"; > + reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; > + qcom,pdc-ranges = <0 480 94>, > + <94 609 31>, <125 63 1>, <126 716 12>; Super weird line break [...] > + > + apps_smmu: iommu@15000000 { > + compatible = "qcom,sar2130p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > + reg = <0x0 0x15000000 0x0 0x100000>; > + #iommu-cells = <2>; > + #global-interrupts = <1>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; dma-coherent? Please check if this is the order they appear in originally, as they're ordered (although on some recent socs it appears they're accidentally sorted by design) > + }; > + > + intc: interrupt-controller@17200000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ > + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */ Please remove these comments [...] > + > + /* > + * Bootloader expects just cache-controller node instead of > + * the typical system-cache-controller > + */ Uh-oh.. > + llcc: cache-controller@19200000 { Konrad