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[79.46.163.127]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a8989196751sm330525766b.121.2024.08.31.07.26.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 31 Aug 2024 07:27:00 -0700 (PDT) Message-ID: <8537f53c-3898-4fa0-8376-de789d5c3ba3@gmail.com> Date: Sat, 31 Aug 2024 16:26:59 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/9] drm/msm/A6xx: Implement preemption for A7XX targets To: Rob Clark Cc: Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Sharat Masetty , Neil Armstrong References: <20240830-preemption-a750-t-v2-0-86aeead2cd80@gmail.com> <20240830-preemption-a750-t-v2-4-86aeead2cd80@gmail.com> Content-Language: en-US From: Antonino Maniscalco In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 8/30/24 10:25 PM, Rob Clark wrote: > On Fri, Aug 30, 2024 at 8:33 AM Antonino Maniscalco > wrote: >> >> This patch implements preemption feature for A6xx targets, this allows >> the GPU to switch to a higher priority ringbuffer if one is ready. A6XX >> hardware as such supports multiple levels of preemption granularities, >> ranging from coarse grained(ringbuffer level) to a more fine grained >> such as draw-call level or a bin boundary level preemption. This patch >> enables the basic preemption level, with more fine grained preemption >> support to follow. >> >> Signed-off-by: Sharat Masetty >> Signed-off-by: Antonino Maniscalco >> Tested-by: Neil Armstrong # on SM8650-QRD >> --- >> drivers/gpu/drm/msm/Makefile | 1 + >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 323 +++++++++++++++++++++- >> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 168 ++++++++++++ >> drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 431 ++++++++++++++++++++++++++++++ >> drivers/gpu/drm/msm/msm_ringbuffer.h | 7 + >> 5 files changed, 921 insertions(+), 9 deletions(-) >> > > [snip] > >> @@ -784,6 +1062,16 @@ static int a6xx_ucode_load(struct msm_gpu *gpu) >> msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow"); >> } >> >> + a6xx_gpu->pwrup_reglist_ptr = msm_gem_kernel_new(gpu->dev, PAGE_SIZE, >> + MSM_BO_WC | MSM_BO_MAP_PRIV, >> + gpu->aspace, &a6xx_gpu->pwrup_reglist_bo, >> + &a6xx_gpu->pwrup_reglist_iova); > > I guess this could also be MSM_BO_GPU_READONLY? > > BR, > -R Besides containing the the actual reglist this buffer also contains the `cpu_gpu_lock` structure which is written by the SQE so adding the `MSM_BO_GPU_READONLY` flag would cause it to fault. Best regards, -- Antonino Maniscalco