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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d80701c94csm14738764a12.85.2024.12.30.06.34.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Dec 2024 06:34:12 -0800 (PST) Message-ID: <85d6703c-ffd2-4a57-93f2-db00f054a864@oss.qualcomm.com> Date: Mon, 30 Dec 2024 15:34:11 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] arm64: dts: qcom: qcs8300: add display dt nodes for MDSS, DPU, DisplayPort and eDP PHY To: Yongxing Mou , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20241226-dts_qcs8300-v2-0-ec8d4fb65cba@quicinc.com> <20241226-dts_qcs8300-v2-1-ec8d4fb65cba@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241226-dts_qcs8300-v2-1-ec8d4fb65cba@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: gJqL-YUmpdT3grODnmLCHg1eRlHts0cz X-Proofpoint-ORIG-GUID: gJqL-YUmpdT3grODnmLCHg1eRlHts0cz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 bulkscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 suspectscore=0 phishscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412300125 On 26.12.2024 11:43 AM, Yongxing Mou wrote: > Add devicetree changes to enable MDSS display-subsystem, > display-controller(DPU), DisplayPort controller and eDP PHY for > Qualcomm QCS8300 platform. > > Signed-off-by: Yongxing Mou > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 204 +++++++++++++++++++++++++++++++++- > 1 file changed, 203 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 80226992a65d867124b33dfa490c3c9ca1030c75..8d88fe4a266432f05192d7ef0dd80362bdbdab85 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -952,6 +952,206 @@ camcc: clock-controller@ade0000 { > #power-domain-cells = <1>; > }; > > + mdss: display-subsystem@ae00000 { > + compatible = "qcom,qcs8300-mdss"; > + reg = <0x0 0x0ae00000 0x0 0x1000>; > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "mdp0-mem", > + "mdp1-mem", > + "cpu-cfg"; Only the CPU path should be ACTIVE_ONLY, the rest should be QCOM_ICC_TAG_ALWAYS > + > + resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>; > + > + power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>; > + > + clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>; Please align the property order with x1e80100.dtsi [...] > + mdss_dp0_phy: phy@aec2a00 { > + compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; > + > + reg = <0x0 0x0aec2a00 0x0 0x19c>, > + <0x0 0x0aec2200 0x0 0xec>, > + <0x0 0x0aec2600 0x0 0xec>, > + <0x0 0x0aec2000 0x0 0x1c8>; > + > + clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; > + clock-names = "aux", > + "cfg_ahb"; > + > + power-domains = <&rpmhpd RPMHPD_MMCX>; The PHYs generally sit on a MX-like rail, please verify this Konrad