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Tue, 03 Dec 2024 07:42:05 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B37g4Lf004198 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 3 Dec 2024 07:42:04 GMT Received: from [10.64.16.135] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 2 Dec 2024 23:41:56 -0800 Message-ID: <86b9a8be-8972-4c19-af0c-da6b3667cbf4@quicinc.com> Date: Tue, 3 Dec 2024 15:41:53 +0800 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/8] drm/msm/dp: Add maximum width limitation for modes To: Dmitry Baryshkov CC: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Kuogee Hsieh" , Vinod Koul , "Kishon Vijay Abraham I" , Linus Walleij , Bartosz Golaszewski , , , , , , , , , References: <20241129-add-displayport-support-for-qcs615-platform-v1-0-09a4338d93ef@quicinc.com> <20241129-add-displayport-support-for-qcs615-platform-v1-6-09a4338d93ef@quicinc.com> <95a78722-8266-4d5d-8d2f-e8efa1aa2e87@quicinc.com> From: Xiangxu Yin In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Q1qP-vfrtkvEYCb2L1IbQAc1v8C0dnsc X-Proofpoint-GUID: Q1qP-vfrtkvEYCb2L1IbQAc1v8C0dnsc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=655 bulkscore=0 impostorscore=0 phishscore=0 suspectscore=0 adultscore=0 mlxscore=0 spamscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412030065 On 12/2/2024 5:32 PM, Dmitry Baryshkov wrote: > On Mon, 2 Dec 2024 at 11:05, Xiangxu Yin wrote: >> >> >> >> On 11/29/2024 9:52 PM, Dmitry Baryshkov wrote: >>> On Fri, 29 Nov 2024 at 09:59, Xiangxu Yin wrote: >>>> >>>> Introduce a maximum width constraint for modes during validation. This >>>> ensures that the modes are filtered based on hardware capabilities, >>>> specifically addressing the line buffer limitations of individual pipes. >>> >>> This doesn't describe, why this is necessary. What does "buffer >>> limitations of individual pipes" mean? >>> If the platforms have hw capabilities like being unable to support 8k >>> or 10k, it should go to platform data >>> >> It's SSPP line buffer limitation for this platform and only support to 2160 mode width. >> Then, shall I add max_width config to struct msm_dp_desc in next patch? for other platform will set defualt value to ‘DP_MAX_WIDTH 7680' > > SSPP line buffer limitations are to be handled in the DPU driver. The > DP driver shouldn't care about those. > Ok, Will drop this part in next patch. >>>> >>>> Signed-off-by: Xiangxu Yin >>>> --- >>>> drivers/gpu/drm/msm/dp/dp_display.c | 3 +++ >>>> drivers/gpu/drm/msm/dp/dp_display.h | 1 + >>>> drivers/gpu/drm/msm/dp/dp_panel.c | 13 +++++++++++++ >>>> drivers/gpu/drm/msm/dp/dp_panel.h | 1 + >>>> 4 files changed, 18 insertions(+) > >