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From: Eric Anholt <eric@anholt.net>
To: Rob Clark <robdclark@gmail.com>, Fritz Koenig <frkoenig@google.com>
Cc: linux-arm-msm <linux-arm-msm@vger.kernel.org>,
	freedreno <freedreno@lists.freedesktop.org>,
	Sean Paul <sean@poorly.run>,
	dri-devel <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH] drm/msm/dpu: Add UBWC support for RGB8888 formats
Date: Thu, 07 Nov 2019 09:30:50 -0800	[thread overview]
Message-ID: <87wocbiofp.fsf@anholt.net> (raw)
In-Reply-To: <CAF6AEGuXv+ePcGtuN2XTFazrMrtyCYMjZOvYn5CZ3bKE2UhVQg@mail.gmail.com>

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Rob Clark <robdclark@gmail.com> writes:

> On Wed, Nov 6, 2019 at 3:26 PM Fritz Koenig <frkoenig@google.com> wrote:
>>
>> Hardware only natively supports BGR8888 UBWC.
>> UBWC support for RGB8888 can be had by pretending
>> that the buffer is BGR.
>
> Just to expand, this aligns with how we handle RGB component order in
> mesa for tiled or tiled+ubwc.  If uncompressed to linear the component
> order is RGB, but in tiled or tiled+ubwc, the component order is
> always the hw "native" order (BGR) regardless of what the outside
> world thinks.  But that detail kinda doesn't matter, it's not like
> generic code is going to understand the tiled or tiled+ubwc format in
> the first place.. and code that does understand it, knows enough to
> know that tiled/tiled+ubwc is always in the native component order.
>
>> Signed-off-by: Fritz Koenig <frkoenig@google.com>
>
> Reviewed-by: Rob Clark <robdclark@gmail.com>

Seems like a reasonable workaround to me, and permissible by our fourcc
modifier rules ("you just have to have one way to address the pixels
given a fourcc and a modifier").

Reviewed-by: Eric Anholt <eric@anholt.net>

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  reply	other threads:[~2019-11-07 17:35 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-06 23:25 [PATCH] drm/msm/dpu: Add UBWC support for RGB8888 formats Fritz Koenig
2019-11-07 16:29 ` Rob Clark
2019-11-07 17:30   ` Eric Anholt [this message]
2019-11-07 17:43     ` Daniel Vetter

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