Re: [PATCH v5 3/4] dt-bindings: PCI: qcom,pcie-sa8255p: Document ECAM compliant PCIe root complex

[Mayank Rana <mayank.rana@oss.qualcomm.com>]

Hi Bjorn

On 7/1/2025 9:52 AM, Bjorn Helgaas wrote:
> On Mon, Jun 16, 2025 at 03:42:58PM -0700, Mayank Rana wrote:
>> Document the required configuration to enable the PCIe root complex on
>> SA8255p, which is managed by firmware using power-domain based handling
>> and configured as ECAM compliant.
> 
>> +    soc {
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +
>> +        pci@1c00000 {
>> +           compatible = "qcom,pcie-sa8255p";
>> +           reg = <0x4 0x00000000 0 0x10000000>;
>> +           device_type = "pci";
>> +           #address-cells = <3>;
>> +           #size-cells = <2>;
>> +           ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>,
>> +                    <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>;
>> +           bus-range = <0x00 0xff>;
>> +           dma-coherent;
>> +           linux,pci-domain = <0>;
>> ...
> 
>> +           pcie@0 {
>> +                   device_type = "pci";
>> +                   reg = <0x0 0x0 0x0 0x0 0x0>;
>> +                   bus-range = <0x01 0xff>;
> 
> This is a Root Port, right?  Why do we need bus-range here?  I assume
> that even without this, the PCI core can detect and manage the bus
> range using PCI_SECONDARY_BUS and PCI_SUBORDINATE_BUS.
On Qualcomm SOCs, root complex based root host bridge is connected to 
single PCIe bridge
with single root port. I have added bus-range based on discussion on 
this thread https://lore.kernel.org/all/20240321-pcie-qcom-bridge-dts-
2-0-1eb790c53e43@linaro.org/
 >> +                   #address-cells = <3>;>> + 
#size-cells = <2>;
>> +                   ranges;
>> +            };
>> +        };
>> +    };
>> -- 
>> 2.25.1
>>
Regards,
Mayank