From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A33E4C4338F for ; Thu, 29 Jul 2021 04:38:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 751C561050 for ; Thu, 29 Jul 2021 04:38:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233541AbhG2Ei2 (ORCPT ); Thu, 29 Jul 2021 00:38:28 -0400 Received: from so254-9.mailgun.net ([198.61.254.9]:32031 "EHLO so254-9.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229485AbhG2Ei1 (ORCPT ); Thu, 29 Jul 2021 00:38:27 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1627533505; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=kEfEwT/ODxxc08E2cVLUhKxwnEHlWMj0LfLS8lLCtPU=; b=td2/P6bU03U0go1NDSm8vKjDksy58ugYEVIoztKZg2jf4bD2Ftk1j8E4/Zy1In094oTSiaAb TnwJSbDqw/OzTVwyj7WZXKkPgNxTnHeBz6TYmzdS17g7Sp2fNi5sQFzqfdzZeLU+R4lwirfp uwBxQt5QC1fiNAFnE5rDhEkOc1w= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-east-1.postgun.com with SMTP id 610230c017c2b4047d9ed642 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Thu, 29 Jul 2021 04:38:24 GMT Sender: saiprakash.ranjan=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id ACE9CC43146; Thu, 29 Jul 2021 04:38:23 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6DFA3C433D3; Thu, 29 Jul 2021 04:38:22 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Thu, 29 Jul 2021 10:08:22 +0530 From: Sai Prakash Ranjan To: Georgi Djakov Cc: Will Deacon , Robin Murphy , Joerg Roedel , Jordan Crouse , Rob Clark , Akhil P Oommen , isaacm@codeaurora.org, iommu@lists.linux-foundation.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno , Kristian H Kristensen , Sean Paul , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org Subject: Re: [PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache In-Reply-To: <20210728140052.GB22887@mms-0441> References: <20210728140052.GB22887@mms-0441> Message-ID: <8b2742c8891abe4fec3664730717a089@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Georgi, On 2021-07-28 19:30, Georgi Djakov wrote: > On Mon, Jan 11, 2021 at 07:45:02PM +0530, Sai Prakash Ranjan wrote: >> commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag") >> removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went >> the memory type setting required for the non-coherent masters to use >> system cache. Now that system cache support for GPU is added, we will >> need to set the right PTE attribute for GPU buffers to be sys cached. >> Without this, the system cache lines are not allocated for GPU. >> >> So the patches in this series introduces a new prot flag IOMMU_LLC, >> renames IO_PGTABLE_QUIRK_ARM_OUTER_WBWA to IO_PGTABLE_QUIRK_PTW_LLC >> and makes GPU the user of this protection flag. > > Hi Sai, > > Thank you for the patchset! Are you planning to refresh it, as it does > not apply anymore? > I was waiting on Will's reply [1]. If there are no changes needed, then I can repost the patch. [1] https://lore.kernel.org/lkml/21239ba603d0bdc4e4c696588a905f88@codeaurora.org/ Thanks, Sai > >> >> The series slightly depends on following 2 patches posted earlier and >> is based on msm-next branch: >> * https://lore.kernel.org/patchwork/patch/1363008/ >> * https://lore.kernel.org/patchwork/patch/1363010/ >> >> Sai Prakash Ranjan (3): >> iommu/io-pgtable: Rename last-level cache quirk to >> IO_PGTABLE_QUIRK_PTW_LLC >> iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag >> drm/msm: Use IOMMU_LLC page protection flag to map gpu buffers >> >> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +++ >> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- >> drivers/gpu/drm/msm/msm_iommu.c | 3 +++ >> drivers/gpu/drm/msm/msm_mmu.h | 4 ++++ >> drivers/iommu/io-pgtable-arm.c | 9 ++++++--- >> include/linux/io-pgtable.h | 6 +++--- >> include/linux/iommu.h | 6 ++++++ >> 7 files changed, 26 insertions(+), 7 deletions(-) >> >> >> base-commit: 00fd44a1a4700718d5d962432b55c09820f7e709 >> -- >> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a >> member >> of Code Aurora Forum, hosted by The Linux Foundation >> -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation