* [PATCH 0/4] clk: qcom: Introduce clocks drivers for SC8380XP
@ 2023-10-25 13:33 Sibi Sankar
2023-10-25 13:33 ` [PATCH 1/4] dt-bindings: clock: qcom: Add SC8380XP GCC clocks Sibi Sankar
` (3 more replies)
0 siblings, 4 replies; 14+ messages in thread
From: Sibi Sankar @ 2023-10-25 13:33 UTC (permalink / raw)
To: andersson, konrad.dybcio, mturquette, sboyd, robh+dt,
krzysztof.kozlowski+dt
Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm,
linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa,
quic_tsoni, Sibi Sankar
This series adds initial clock support for the Qualcomm SC8380XP platform, aka Snapdragon X Elite.
Dependencies: None
Release Link: https://www.qualcomm.com/news/releases/2023/10/qualcomm-unleashes-snapdragon-x-elite--the-ai-super-charged-plat
Rajendra Nayak (4):
dt-bindings: clock: qcom: Add SC8380XP GCC clocks
clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP
dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for SC8380XP
clk: qcom: rpmh: Add support for SC8380XP rpmh clocks
.../bindings/clock/qcom,rpmhcc.yaml | 1 +
.../bindings/clock/qcom,sc8380xp-gcc.yaml | 72 +
drivers/clk/qcom/Kconfig | 10 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 26 +
drivers/clk/qcom/gcc-sc8380xp.c | 6812 +++++++++++++++++
include/dt-bindings/clock/qcom,sc8380xp-gcc.h | 485 ++
7 files changed, 7407 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8380xp-gcc.yaml
create mode 100644 drivers/clk/qcom/gcc-sc8380xp.c
create mode 100644 include/dt-bindings/clock/qcom,sc8380xp-gcc.h
--
2.17.1
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 1/4] dt-bindings: clock: qcom: Add SC8380XP GCC clocks 2023-10-25 13:33 [PATCH 0/4] clk: qcom: Introduce clocks drivers for SC8380XP Sibi Sankar @ 2023-10-25 13:33 ` Sibi Sankar 2023-10-27 8:20 ` Krzysztof Kozlowski 2023-10-25 13:33 ` [PATCH 3/4] dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for SC8380XP Sibi Sankar ` (2 subsequent siblings) 3 siblings, 1 reply; 14+ messages in thread From: Sibi Sankar @ 2023-10-25 13:33 UTC (permalink / raw) To: andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni, Sibi Sankar From: Rajendra Nayak <quic_rjendra@quicinc.com> Add device tree bindings for global clock controller on SC8380XP SoCs. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> --- .../bindings/clock/qcom,sc8380xp-gcc.yaml | 72 +++ include/dt-bindings/clock/qcom,sc8380xp-gcc.h | 485 ++++++++++++++++++ 2 files changed, 557 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc8380xp-gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,sc8380xp-gcc.h diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8380xp-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8380xp-gcc.yaml new file mode 100644 index 000000000000..8b231e1d25ac --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc8380xp-gcc.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc8380xp-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on SC8380XP + +maintainers: + - Rajendra Nayak <quic_rjendra@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on SC8380XP + + See also:: include/dt-bindings/clock/qcom,sc8380xp-gcc.h + +properties: + compatible: + const: qcom,sc8380xp-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIe 3 pipe clock + - description: PCIe 4 pipe clock + - description: PCIe 5 pipe clock + - description: PCIe 6a pipe clock + - description: PCIe 6b pipe clock + - description: USB QMP Phy 0 clock source + - description: USB QMP Phy 1 clock source + - description: USB QMP Phy 2 clock source + + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + +required: + - compatible + - clocks + - power-domains + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/power/qcom,rpmhpd.h> + clock-controller@100000 { + compatible = "qcom,sc8380xp-gcc"; + reg = <0x00100000 0x200000>; + clocks = <&bi_tcxo_div2>, + <&sleep_clk>, + <&pcie3_phy>, + <&pcie4_phy>, + <&pcie5_phy>, + <&pcie6a_phy>, + <&pcie6b_phy>, + <&usb_1_ss0_qmpphy 0>, + <&usb_1_ss1_qmpphy 1>, + <&usb_1_ss2_qmpphy 2>; + power-domains = <&rpmhpd RPMHPD_CX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,sc8380xp-gcc.h b/include/dt-bindings/clock/qcom,sc8380xp-gcc.h new file mode 100644 index 000000000000..c4cf449accf8 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sc8380xp-gcc.h @@ -0,0 +1,485 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC8380XP_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SC8380XP_H + +/* GCC clocks */ +#define GCC_AGGRE_NOC_USB_NORTH_AXI_CLK 0 +#define GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK 1 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 2 +#define GCC_AGGRE_USB2_PRIM_AXI_CLK 3 +#define GCC_AGGRE_USB3_MP_AXI_CLK 4 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5 +#define GCC_AGGRE_USB3_SEC_AXI_CLK 6 +#define GCC_AGGRE_USB3_TERT_AXI_CLK 7 +#define GCC_AGGRE_USB4_0_AXI_CLK 8 +#define GCC_AGGRE_USB4_1_AXI_CLK 9 +#define GCC_AGGRE_USB4_2_AXI_CLK 10 +#define GCC_AGGRE_USB_NOC_AXI_CLK 11 +#define GCC_AV1E_AHB_CLK 12 +#define GCC_AV1E_AXI_CLK 13 +#define GCC_AV1E_XO_CLK 14 +#define GCC_BOOT_ROM_AHB_CLK 15 +#define GCC_CAMERA_AHB_CLK 16 +#define GCC_CAMERA_HF_AXI_CLK 17 +#define GCC_CAMERA_SF_AXI_CLK 18 +#define GCC_CAMERA_XO_CLK 19 +#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 20 +#define GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK 21 +#define GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK 22 +#define GCC_CFG_NOC_USB2_PRIM_AXI_CLK 23 +#define GCC_CFG_NOC_USB3_MP_AXI_CLK 24 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 25 +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 26 +#define GCC_CFG_NOC_USB3_TERT_AXI_CLK 27 +#define GCC_CFG_NOC_USB_ANOC_AHB_CLK 28 +#define GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK 29 +#define GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK 30 +#define GCC_CNOC_PCIE1_TUNNEL_CLK 31 +#define GCC_CNOC_PCIE2_TUNNEL_CLK 32 +#define GCC_CNOC_PCIE_NORTH_SF_AXI_CLK 33 +#define GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK 34 +#define GCC_CNOC_PCIE_TUNNEL_CLK 35 +#define GCC_DDRSS_GPU_AXI_CLK 36 +#define GCC_DISP_AHB_CLK 37 +#define GCC_DISP_HF_AXI_CLK 38 +#define GCC_DISP_XO_CLK 39 +#define GCC_GP1_CLK 40 +#define GCC_GP1_CLK_SRC 41 +#define GCC_GP2_CLK 42 +#define GCC_GP2_CLK_SRC 43 +#define GCC_GP3_CLK 44 +#define GCC_GP3_CLK_SRC 45 +#define GCC_GPLL0 46 +#define GCC_GPLL0_OUT_EVEN 47 +#define GCC_GPLL4 48 +#define GCC_GPLL7 49 +#define GCC_GPLL8 50 +#define GCC_GPLL9 51 +#define GCC_GPU_CFG_AHB_CLK 52 +#define GCC_GPU_GPLL0_CPH_CLK_SRC 53 +#define GCC_GPU_GPLL0_DIV_CPH_CLK_SRC 54 +#define GCC_GPU_MEMNOC_GFX_CLK 55 +#define GCC_GPU_SNOC_DVM_GFX_CLK 56 +#define GCC_PCIE0_PHY_RCHNG_CLK 57 +#define GCC_PCIE1_PHY_RCHNG_CLK 58 +#define GCC_PCIE2_PHY_RCHNG_CLK 59 +#define GCC_PCIE_0_AUX_CLK 60 +#define GCC_PCIE_0_AUX_CLK_SRC 61 +#define GCC_PCIE_0_CFG_AHB_CLK 62 +#define GCC_PCIE_0_MSTR_AXI_CLK 63 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 64 +#define GCC_PCIE_0_PIPE_CLK 65 +#define GCC_PCIE_0_SLV_AXI_CLK 66 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 67 +#define GCC_PCIE_1_AUX_CLK 68 +#define GCC_PCIE_1_AUX_CLK_SRC 69 +#define GCC_PCIE_1_CFG_AHB_CLK 70 +#define GCC_PCIE_1_MSTR_AXI_CLK 71 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 72 +#define GCC_PCIE_1_PIPE_CLK 73 +#define GCC_PCIE_1_SLV_AXI_CLK 74 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 75 +#define GCC_PCIE_2_AUX_CLK 76 +#define GCC_PCIE_2_AUX_CLK_SRC 77 +#define GCC_PCIE_2_CFG_AHB_CLK 78 +#define GCC_PCIE_2_MSTR_AXI_CLK 79 +#define GCC_PCIE_2_PHY_RCHNG_CLK_SRC 80 +#define GCC_PCIE_2_PIPE_CLK 81 +#define GCC_PCIE_2_SLV_AXI_CLK 82 +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 83 +#define GCC_PCIE_3_AUX_CLK 84 +#define GCC_PCIE_3_AUX_CLK_SRC 85 +#define GCC_PCIE_3_CFG_AHB_CLK 86 +#define GCC_PCIE_3_MSTR_AXI_CLK 87 +#define GCC_PCIE_3_PHY_AUX_CLK 88 +#define GCC_PCIE_3_PHY_RCHNG_CLK 89 +#define GCC_PCIE_3_PHY_RCHNG_CLK_SRC 90 +#define GCC_PCIE_3_PIPE_CLK 91 +#define GCC_PCIE_3_PIPE_DIV_CLK_SRC 92 +#define GCC_PCIE_3_PIPEDIV2_CLK 93 +#define GCC_PCIE_3_SLV_AXI_CLK 94 +#define GCC_PCIE_3_SLV_Q2A_AXI_CLK 95 +#define GCC_PCIE_4_AUX_CLK 96 +#define GCC_PCIE_4_AUX_CLK_SRC 97 +#define GCC_PCIE_4_CFG_AHB_CLK 98 +#define GCC_PCIE_4_MSTR_AXI_CLK 99 +#define GCC_PCIE_4_PHY_RCHNG_CLK 100 +#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 101 +#define GCC_PCIE_4_PIPE_CLK 102 +#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 103 +#define GCC_PCIE_4_PIPEDIV2_CLK 104 +#define GCC_PCIE_4_SLV_AXI_CLK 105 +#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 106 +#define GCC_PCIE_5_AUX_CLK 107 +#define GCC_PCIE_5_AUX_CLK_SRC 108 +#define GCC_PCIE_5_CFG_AHB_CLK 109 +#define GCC_PCIE_5_MSTR_AXI_CLK 110 +#define GCC_PCIE_5_PHY_RCHNG_CLK 111 +#define GCC_PCIE_5_PHY_RCHNG_CLK_SRC 112 +#define GCC_PCIE_5_PIPE_CLK 113 +#define GCC_PCIE_5_PIPE_DIV_CLK_SRC 114 +#define GCC_PCIE_5_PIPEDIV2_CLK 115 +#define GCC_PCIE_5_SLV_AXI_CLK 116 +#define GCC_PCIE_5_SLV_Q2A_AXI_CLK 117 +#define GCC_PCIE_6A_AUX_CLK 118 +#define GCC_PCIE_6A_AUX_CLK_SRC 119 +#define GCC_PCIE_6A_CFG_AHB_CLK 120 +#define GCC_PCIE_6A_MSTR_AXI_CLK 121 +#define GCC_PCIE_6A_PHY_AUX_CLK 122 +#define GCC_PCIE_6A_PHY_RCHNG_CLK 123 +#define GCC_PCIE_6A_PHY_RCHNG_CLK_SRC 124 +#define GCC_PCIE_6A_PIPE_CLK 125 +#define GCC_PCIE_6A_PIPE_DIV_CLK_SRC 126 +#define GCC_PCIE_6A_PIPEDIV2_CLK 127 +#define GCC_PCIE_6A_SLV_AXI_CLK 128 +#define GCC_PCIE_6A_SLV_Q2A_AXI_CLK 129 +#define GCC_PCIE_6B_AUX_CLK 130 +#define GCC_PCIE_6B_AUX_CLK_SRC 131 +#define GCC_PCIE_6B_CFG_AHB_CLK 132 +#define GCC_PCIE_6B_MSTR_AXI_CLK 133 +#define GCC_PCIE_6B_PHY_AUX_CLK 134 +#define GCC_PCIE_6B_PHY_RCHNG_CLK 135 +#define GCC_PCIE_6B_PHY_RCHNG_CLK_SRC 136 +#define GCC_PCIE_6B_PIPE_CLK 137 +#define GCC_PCIE_6B_PIPE_DIV_CLK_SRC 138 +#define GCC_PCIE_6B_PIPEDIV2_CLK 139 +#define GCC_PCIE_6B_SLV_AXI_CLK 140 +#define GCC_PCIE_6B_SLV_Q2A_AXI_CLK 141 +#define GCC_PCIE_RSCC_AHB_CLK 142 +#define GCC_PCIE_RSCC_XO_CLK 143 +#define GCC_PCIE_RSCC_XO_CLK_SRC 144 +#define GCC_PDM2_CLK 145 +#define GCC_PDM2_CLK_SRC 146 +#define GCC_PDM_AHB_CLK 147 +#define GCC_PDM_XO4_CLK 148 +#define GCC_QMIP_AV1E_AHB_CLK 149 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 150 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 151 +#define GCC_QMIP_DISP_AHB_CLK 152 +#define GCC_QMIP_GPU_AHB_CLK 153 +#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 154 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 155 +#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 156 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 157 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 158 +#define GCC_QUPV3_WRAP0_CORE_CLK 159 +#define GCC_QUPV3_WRAP0_QSPI_S2_CLK 160 +#define GCC_QUPV3_WRAP0_QSPI_S3_CLK 161 +#define GCC_QUPV3_WRAP0_S0_CLK 162 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 163 +#define GCC_QUPV3_WRAP0_S1_CLK 164 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 165 +#define GCC_QUPV3_WRAP0_S2_CLK 166 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 167 +#define GCC_QUPV3_WRAP0_S2_DIV_CLK_SRC 168 +#define GCC_QUPV3_WRAP0_S3_CLK 169 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 170 +#define GCC_QUPV3_WRAP0_S3_DIV_CLK_SRC 171 +#define GCC_QUPV3_WRAP0_S4_CLK 172 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 173 +#define GCC_QUPV3_WRAP0_S5_CLK 174 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 175 +#define GCC_QUPV3_WRAP0_S6_CLK 176 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 177 +#define GCC_QUPV3_WRAP0_S7_CLK 178 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 179 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 180 +#define GCC_QUPV3_WRAP1_CORE_CLK 181 +#define GCC_QUPV3_WRAP1_QSPI_S2_CLK 182 +#define GCC_QUPV3_WRAP1_QSPI_S3_CLK 183 +#define GCC_QUPV3_WRAP1_S0_CLK 184 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 185 +#define GCC_QUPV3_WRAP1_S1_CLK 186 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 187 +#define GCC_QUPV3_WRAP1_S2_CLK 188 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 189 +#define GCC_QUPV3_WRAP1_S2_DIV_CLK_SRC 190 +#define GCC_QUPV3_WRAP1_S3_CLK 191 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 192 +#define GCC_QUPV3_WRAP1_S3_DIV_CLK_SRC 193 +#define GCC_QUPV3_WRAP1_S4_CLK 194 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 195 +#define GCC_QUPV3_WRAP1_S5_CLK 196 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 197 +#define GCC_QUPV3_WRAP1_S6_CLK 198 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 199 +#define GCC_QUPV3_WRAP1_S7_CLK 200 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 201 +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 202 +#define GCC_QUPV3_WRAP2_CORE_CLK 203 +#define GCC_QUPV3_WRAP2_QSPI_S2_CLK 204 +#define GCC_QUPV3_WRAP2_QSPI_S3_CLK 205 +#define GCC_QUPV3_WRAP2_S0_CLK 206 +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 207 +#define GCC_QUPV3_WRAP2_S1_CLK 208 +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 209 +#define GCC_QUPV3_WRAP2_S2_CLK 210 +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 211 +#define GCC_QUPV3_WRAP2_S2_DIV_CLK_SRC 212 +#define GCC_QUPV3_WRAP2_S3_CLK 213 +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 214 +#define GCC_QUPV3_WRAP2_S3_DIV_CLK_SRC 215 +#define GCC_QUPV3_WRAP2_S4_CLK 216 +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 217 +#define GCC_QUPV3_WRAP2_S5_CLK 218 +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 219 +#define GCC_QUPV3_WRAP2_S6_CLK 220 +#define GCC_QUPV3_WRAP2_S6_CLK_SRC 221 +#define GCC_QUPV3_WRAP2_S7_CLK 222 +#define GCC_QUPV3_WRAP2_S7_CLK_SRC 223 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 224 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 225 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 226 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 227 +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 228 +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 229 +#define GCC_SDCC2_AHB_CLK 230 +#define GCC_SDCC2_APPS_CLK 231 +#define GCC_SDCC2_APPS_CLK_SRC 232 +#define GCC_SDCC4_AHB_CLK 233 +#define GCC_SDCC4_APPS_CLK 234 +#define GCC_SDCC4_APPS_CLK_SRC 235 +#define GCC_SYS_NOC_USB_AXI_CLK 236 +#define GCC_UFS_PHY_AHB_CLK 237 +#define GCC_UFS_PHY_AXI_CLK 238 +#define GCC_UFS_PHY_AXI_CLK_SRC 239 +#define GCC_UFS_PHY_ICE_CORE_CLK 240 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 241 +#define GCC_UFS_PHY_PHY_AUX_CLK 242 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 243 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 244 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 245 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 246 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 247 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 248 +#define GCC_USB20_MASTER_CLK 249 +#define GCC_USB20_MASTER_CLK_SRC 250 +#define GCC_USB20_MOCK_UTMI_CLK 251 +#define GCC_USB20_MOCK_UTMI_CLK_SRC 252 +#define GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 253 +#define GCC_USB20_SLEEP_CLK 254 +#define GCC_USB30_MP_MASTER_CLK 255 +#define GCC_USB30_MP_MASTER_CLK_SRC 256 +#define GCC_USB30_MP_MOCK_UTMI_CLK 257 +#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 258 +#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 259 +#define GCC_USB30_MP_SLEEP_CLK 260 +#define GCC_USB30_PRIM_MASTER_CLK 261 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 262 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 263 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 264 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 265 +#define GCC_USB30_PRIM_SLEEP_CLK 266 +#define GCC_USB30_SEC_MASTER_CLK 267 +#define GCC_USB30_SEC_MASTER_CLK_SRC 268 +#define GCC_USB30_SEC_MOCK_UTMI_CLK 269 +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 270 +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 271 +#define GCC_USB30_SEC_SLEEP_CLK 272 +#define GCC_USB30_TERT_MASTER_CLK 273 +#define GCC_USB30_TERT_MASTER_CLK_SRC 274 +#define GCC_USB30_TERT_MOCK_UTMI_CLK 275 +#define GCC_USB30_TERT_MOCK_UTMI_CLK_SRC 276 +#define GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC 277 +#define GCC_USB30_TERT_SLEEP_CLK 278 +#define GCC_USB3_MP_PHY_AUX_CLK 279 +#define GCC_USB3_MP_PHY_AUX_CLK_SRC 280 +#define GCC_USB3_MP_PHY_COM_AUX_CLK 281 +#define GCC_USB3_MP_PHY_PIPE_0_CLK 282 +#define GCC_USB3_MP_PHY_PIPE_1_CLK 283 +#define GCC_USB3_PRIM_PHY_AUX_CLK 284 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 285 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 286 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 287 +#define GCC_USB3_SEC_PHY_AUX_CLK 288 +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 289 +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 290 +#define GCC_USB3_SEC_PHY_PIPE_CLK 291 +#define GCC_USB3_TERT_PHY_AUX_CLK 292 +#define GCC_USB3_TERT_PHY_AUX_CLK_SRC 293 +#define GCC_USB3_TERT_PHY_COM_AUX_CLK 294 +#define GCC_USB3_TERT_PHY_PIPE_CLK 295 +#define GCC_USB4_0_CFG_AHB_CLK 296 +#define GCC_USB4_0_DP0_CLK 297 +#define GCC_USB4_0_DP1_CLK 298 +#define GCC_USB4_0_MASTER_CLK 299 +#define GCC_USB4_0_MASTER_CLK_SRC 300 +#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK 301 +#define GCC_USB4_0_PHY_PCIE_PIPE_CLK 302 +#define GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC 303 +#define GCC_USB4_0_PHY_RX0_CLK 304 +#define GCC_USB4_0_PHY_RX1_CLK 305 +#define GCC_USB4_0_PHY_USB_PIPE_CLK 306 +#define GCC_USB4_0_SB_IF_CLK 307 +#define GCC_USB4_0_SB_IF_CLK_SRC 308 +#define GCC_USB4_0_SYS_CLK 309 +#define GCC_USB4_0_TMU_CLK 310 +#define GCC_USB4_0_TMU_CLK_SRC 311 +#define GCC_USB4_1_CFG_AHB_CLK 312 +#define GCC_USB4_1_DP0_CLK 313 +#define GCC_USB4_1_DP1_CLK 314 +#define GCC_USB4_1_MASTER_CLK 315 +#define GCC_USB4_1_MASTER_CLK_SRC 316 +#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 317 +#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 318 +#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 319 +#define GCC_USB4_1_PHY_RX0_CLK 320 +#define GCC_USB4_1_PHY_RX1_CLK 321 +#define GCC_USB4_1_PHY_USB_PIPE_CLK 322 +#define GCC_USB4_1_SB_IF_CLK 323 +#define GCC_USB4_1_SB_IF_CLK_SRC 324 +#define GCC_USB4_1_SYS_CLK 325 +#define GCC_USB4_1_TMU_CLK 326 +#define GCC_USB4_1_TMU_CLK_SRC 327 +#define GCC_USB4_2_CFG_AHB_CLK 328 +#define GCC_USB4_2_DP0_CLK 329 +#define GCC_USB4_2_DP1_CLK 330 +#define GCC_USB4_2_MASTER_CLK 331 +#define GCC_USB4_2_MASTER_CLK_SRC 332 +#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK 333 +#define GCC_USB4_2_PHY_PCIE_PIPE_CLK 334 +#define GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC 335 +#define GCC_USB4_2_PHY_RX0_CLK 336 +#define GCC_USB4_2_PHY_RX1_CLK 337 +#define GCC_USB4_2_PHY_USB_PIPE_CLK 338 +#define GCC_USB4_2_SB_IF_CLK 339 +#define GCC_USB4_2_SB_IF_CLK_SRC 340 +#define GCC_USB4_2_SYS_CLK 341 +#define GCC_USB4_2_TMU_CLK 342 +#define GCC_USB4_2_TMU_CLK_SRC 343 +#define GCC_VIDEO_AHB_CLK 344 +#define GCC_VIDEO_AXI0_CLK 345 +#define GCC_VIDEO_AXI1_CLK 346 +#define GCC_VIDEO_XO_CLK 347 +#define GCC_PCIE_3_PIPE_CLK_SRC 348 +#define GCC_PCIE_4_PIPE_CLK_SRC 349 +#define GCC_PCIE_5_PIPE_CLK_SRC 350 +#define GCC_PCIE_6A_PIPE_CLK_SRC 351 +#define GCC_PCIE_6B_PIPE_CLK_SRC 352 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353 +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354 +#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355 + +/* GCC power domains */ +#define GCC_PCIE_0_TUNNEL_GDSC 0 +#define GCC_PCIE_1_TUNNEL_GDSC 1 +#define GCC_PCIE_2_TUNNEL_GDSC 2 +#define GCC_PCIE_3_GDSC 3 +#define GCC_PCIE_3_PHY_GDSC 4 +#define GCC_PCIE_4_GDSC 5 +#define GCC_PCIE_4_PHY_GDSC 6 +#define GCC_PCIE_5_GDSC 7 +#define GCC_PCIE_5_PHY_GDSC 8 +#define GCC_PCIE_6_PHY_GDSC 9 +#define GCC_PCIE_6A_GDSC 10 +#define GCC_PCIE_6B_GDSC 11 +#define GCC_UFS_MEM_PHY_GDSC 12 +#define GCC_UFS_PHY_GDSC 13 +#define GCC_USB20_PRIM_GDSC 14 +#define GCC_USB30_MP_GDSC 15 +#define GCC_USB30_PRIM_GDSC 16 +#define GCC_USB30_SEC_GDSC 17 +#define GCC_USB30_TERT_GDSC 18 +#define GCC_USB3_MP_SS0_PHY_GDSC 19 +#define GCC_USB3_MP_SS1_PHY_GDSC 20 +#define GCC_USB4_0_GDSC 21 +#define GCC_USB4_1_GDSC 22 +#define GCC_USB4_2_GDSC 23 +#define GCC_USB_0_PHY_GDSC 24 +#define GCC_USB_1_PHY_GDSC 25 +#define GCC_USB_2_PHY_GDSC 26 + +/* GCC resets */ +#define GCC_AV1E_BCR 0 +#define GCC_CAMERA_BCR 1 +#define GCC_DISPLAY_BCR 2 +#define GCC_GPU_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_0_TUNNEL_BCR 8 +#define GCC_PCIE_1_LINK_DOWN_BCR 9 +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 10 +#define GCC_PCIE_1_PHY_BCR 11 +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 12 +#define GCC_PCIE_1_TUNNEL_BCR 13 +#define GCC_PCIE_2_LINK_DOWN_BCR 14 +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 15 +#define GCC_PCIE_2_PHY_BCR 16 +#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 17 +#define GCC_PCIE_2_TUNNEL_BCR 18 +#define GCC_PCIE_3_BCR 19 +#define GCC_PCIE_3_LINK_DOWN_BCR 20 +#define GCC_PCIE_3_NOCSR_COM_PHY_BCR 21 +#define GCC_PCIE_3_PHY_BCR 22 +#define GCC_PCIE_3_PHY_NOCSR_COM_PHY_BCR 23 +#define GCC_PCIE_4_BCR 24 +#define GCC_PCIE_4_LINK_DOWN_BCR 25 +#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 26 +#define GCC_PCIE_4_PHY_BCR 27 +#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 28 +#define GCC_PCIE_5_BCR 29 +#define GCC_PCIE_5_LINK_DOWN_BCR 30 +#define GCC_PCIE_5_NOCSR_COM_PHY_BCR 31 +#define GCC_PCIE_5_PHY_BCR 32 +#define GCC_PCIE_5_PHY_NOCSR_COM_PHY_BCR 33 +#define GCC_PCIE_6A_BCR 34 +#define GCC_PCIE_6A_LINK_DOWN_BCR 35 +#define GCC_PCIE_6A_NOCSR_COM_PHY_BCR 36 +#define GCC_PCIE_6A_PHY_BCR 37 +#define GCC_PCIE_6A_PHY_NOCSR_COM_PHY_BCR 38 +#define GCC_PCIE_6B_BCR 39 +#define GCC_PCIE_6B_LINK_DOWN_BCR 40 +#define GCC_PCIE_6B_NOCSR_COM_PHY_BCR 41 +#define GCC_PCIE_6B_PHY_BCR 42 +#define GCC_PCIE_6B_PHY_NOCSR_COM_PHY_BCR 43 +#define GCC_PCIE_PHY_BCR 44 +#define GCC_PCIE_PHY_CFG_AHB_BCR 45 +#define GCC_PCIE_PHY_COM_BCR 46 +#define GCC_PCIE_RSCC_BCR 47 +#define GCC_PDM_BCR 48 +#define GCC_QUPV3_WRAPPER_0_BCR 49 +#define GCC_QUPV3_WRAPPER_1_BCR 50 +#define GCC_QUPV3_WRAPPER_2_BCR 51 +#define GCC_QUSB2PHY_HS0_MP_BCR 52 +#define GCC_QUSB2PHY_HS1_MP_BCR 53 +#define GCC_QUSB2PHY_PRIM_BCR 54 +#define GCC_QUSB2PHY_SEC_BCR 55 +#define GCC_QUSB2PHY_TERT_BCR 56 +#define GCC_QUSB2PHY_USB20_HS_BCR 57 +#define GCC_SDCC2_BCR 58 +#define GCC_SDCC4_BCR 59 +#define GCC_UFS_PHY_BCR 60 +#define GCC_USB20_PRIM_BCR 61 +#define GCC_USB30_MP_BCR 62 +#define GCC_USB30_PRIM_BCR 63 +#define GCC_USB30_SEC_BCR 64 +#define GCC_USB30_TERT_BCR 65 +#define GCC_USB3_MP_SS0_PHY_BCR 66 +#define GCC_USB3_MP_SS1_PHY_BCR 67 +#define GCC_USB3_PHY_PRIM_BCR 68 +#define GCC_USB3_PHY_SEC_BCR 69 +#define GCC_USB3_PHY_TERT_BCR 70 +#define GCC_USB3_UNIPHY_MP0_BCR 71 +#define GCC_USB3_UNIPHY_MP1_BCR 72 +#define GCC_USB3PHY_PHY_PRIM_BCR 73 +#define GCC_USB3PHY_PHY_SEC_BCR 74 +#define GCC_USB3PHY_PHY_TERT_BCR 75 +#define GCC_USB3UNIPHY_PHY_MP0_BCR 76 +#define GCC_USB3UNIPHY_PHY_MP1_BCR 77 +#define GCC_USB4_0_BCR 78 +#define GCC_USB4_0_DP0_PHY_PRIM_BCR 79 +#define GCC_USB4_1_DP0_PHY_SEC_BCR 80 +#define GCC_USB4_2_DP0_PHY_TERT_BCR 81 +#define GCC_USB4_1_BCR 82 +#define GCC_USB4_2_BCR 83 +#define GCC_USB_0_PHY_BCR 84 +#define GCC_USB_1_PHY_BCR 85 +#define GCC_USB_2_PHY_BCR 86 +#define GCC_VIDEO_BCR 87 +#endif -- 2.17.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/4] dt-bindings: clock: qcom: Add SC8380XP GCC clocks 2023-10-25 13:33 ` [PATCH 1/4] dt-bindings: clock: qcom: Add SC8380XP GCC clocks Sibi Sankar @ 2023-10-27 8:20 ` Krzysztof Kozlowski 0 siblings, 0 replies; 14+ messages in thread From: Krzysztof Kozlowski @ 2023-10-27 8:20 UTC (permalink / raw) To: Sibi Sankar, andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni On 25/10/2023 15:33, Sibi Sankar wrote: > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > Add device tree bindings for global clock controller on SC8380XP SoCs. > > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> > Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com> > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/4] dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for SC8380XP 2023-10-25 13:33 [PATCH 0/4] clk: qcom: Introduce clocks drivers for SC8380XP Sibi Sankar 2023-10-25 13:33 ` [PATCH 1/4] dt-bindings: clock: qcom: Add SC8380XP GCC clocks Sibi Sankar @ 2023-10-25 13:33 ` Sibi Sankar 2023-10-27 8:20 ` Krzysztof Kozlowski 2023-10-25 13:33 ` [PATCH 4/4] clk: qcom: rpmh: Add support for SC8380XP rpmh clocks Sibi Sankar [not found] ` <20231025133320.4720-3-quic_sibis@quicinc.com> 3 siblings, 1 reply; 14+ messages in thread From: Sibi Sankar @ 2023-10-25 13:33 UTC (permalink / raw) To: andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni, Sibi Sankar From: Rajendra Nayak <quic_rjendra@quicinc.com> Add bindings and update documentation for clock rpmh driver on SC8380XP SoCs. Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index 4eb5e59f6772..b1faf99b75c6 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -23,6 +23,7 @@ properties: - qcom,sc7280-rpmh-clk - qcom,sc8180x-rpmh-clk - qcom,sc8280xp-rpmh-clk + - qcom,sc8380xp-rpmh-clk - qcom,sdm670-rpmh-clk - qcom,sdm845-rpmh-clk - qcom,sdx55-rpmh-clk -- 2.17.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 3/4] dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for SC8380XP 2023-10-25 13:33 ` [PATCH 3/4] dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for SC8380XP Sibi Sankar @ 2023-10-27 8:20 ` Krzysztof Kozlowski 0 siblings, 0 replies; 14+ messages in thread From: Krzysztof Kozlowski @ 2023-10-27 8:20 UTC (permalink / raw) To: Sibi Sankar, andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni On 25/10/2023 15:33, Sibi Sankar wrote: > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > Add bindings and update documentation for clock rpmh driver on SC8380XP > SoCs. > > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- This is an automated instruction, just in case, because many review tags are being ignored. If you know the process, you can skip it (please do not feel offended by me posting it here - no bad intentions intended). If you do not know the process, here is a short explanation: Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions, under or above your Signed-off-by tag. Tag is "received", when provided in a message replied to you on the mailing list. Tools like b4 can help here. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for tags received on the version they apply. https://elixir.bootlin.com/linux/v6.5-rc3/source/Documentation/process/submitting-patches.rst#L577 Best regards, Krzysztof ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 4/4] clk: qcom: rpmh: Add support for SC8380XP rpmh clocks 2023-10-25 13:33 [PATCH 0/4] clk: qcom: Introduce clocks drivers for SC8380XP Sibi Sankar 2023-10-25 13:33 ` [PATCH 1/4] dt-bindings: clock: qcom: Add SC8380XP GCC clocks Sibi Sankar 2023-10-25 13:33 ` [PATCH 3/4] dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for SC8380XP Sibi Sankar @ 2023-10-25 13:33 ` Sibi Sankar 2023-10-25 20:38 ` Bryan O'Donoghue 2023-10-26 11:07 ` Konrad Dybcio [not found] ` <20231025133320.4720-3-quic_sibis@quicinc.com> 3 siblings, 2 replies; 14+ messages in thread From: Sibi Sankar @ 2023-10-25 13:33 UTC (permalink / raw) To: andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni, Sibi Sankar From: Rajendra Nayak <quic_rjendra@quicinc.com> Adds the RPMH clocks present in SC8380XP SoC Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> --- drivers/clk/qcom/clk-rpmh.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 5d853fd43294..7f6d5f98957b 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -372,6 +372,9 @@ DEFINE_CLK_RPMH_VRM(clk3, _a1, "clka3", 1); DEFINE_CLK_RPMH_VRM(clk4, _a1, "clka4", 1); DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1); +DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2); +DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2); +DEFINE_CLK_RPMH_VRM(clk5, _a2, "clka5", 2); DEFINE_CLK_RPMH_VRM(clk6, _a2, "clka6", 2); DEFINE_CLK_RPMH_VRM(clk7, _a2, "clka7", 2); DEFINE_CLK_RPMH_VRM(clk8, _a2, "clka8", 2); @@ -737,6 +740,28 @@ static const struct clk_rpmh_desc clk_rpmh_sm4450 = { .num_clks = ARRAY_SIZE(sm4450_rpmh_clocks), }; +static struct clk_hw *sc8380xp_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, + [RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2.hw, + [RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_ao.hw, + [RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2.hw, + [RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_ao.hw, + [RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2.hw, + [RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_ao.hw, + [RPMH_RF_CLK3] = &clk_rpmh_clk3_a2.hw, + [RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a2_ao.hw, + [RPMH_RF_CLK4] = &clk_rpmh_clk4_a2.hw, + [RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_ao.hw, + [RPMH_RF_CLK5] = &clk_rpmh_clk5_a2.hw, + [RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sc8380xp = { + .clks = sc8380xp_rpmh_clocks, + .num_clks = ARRAY_SIZE(sc8380xp_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -825,6 +850,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp}, + { .compatible = "qcom,sc8380xp-rpmh-clk", .data = &clk_rpmh_sc8380xp}, { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, { .compatible = "qcom,sdm670-rpmh-clk", .data = &clk_rpmh_sdm670}, { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, -- 2.17.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 4/4] clk: qcom: rpmh: Add support for SC8380XP rpmh clocks 2023-10-25 13:33 ` [PATCH 4/4] clk: qcom: rpmh: Add support for SC8380XP rpmh clocks Sibi Sankar @ 2023-10-25 20:38 ` Bryan O'Donoghue 2023-10-26 11:07 ` Konrad Dybcio 1 sibling, 0 replies; 14+ messages in thread From: Bryan O'Donoghue @ 2023-10-25 20:38 UTC (permalink / raw) To: Sibi Sankar, andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni On 25/10/2023 14:33, Sibi Sankar wrote: > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > Adds the RPMH clocks present in SC8380XP SoC > > Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- This looks pretty straight forward. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 4/4] clk: qcom: rpmh: Add support for SC8380XP rpmh clocks 2023-10-25 13:33 ` [PATCH 4/4] clk: qcom: rpmh: Add support for SC8380XP rpmh clocks Sibi Sankar 2023-10-25 20:38 ` Bryan O'Donoghue @ 2023-10-26 11:07 ` Konrad Dybcio 1 sibling, 0 replies; 14+ messages in thread From: Konrad Dybcio @ 2023-10-26 11:07 UTC (permalink / raw) To: Sibi Sankar, andersson, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni On 10/25/23 15:33, Sibi Sankar wrote: > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > Adds the RPMH clocks present in SC8380XP SoC > > Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <20231025133320.4720-3-quic_sibis@quicinc.com>]
* Re: [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP [not found] ` <20231025133320.4720-3-quic_sibis@quicinc.com> @ 2023-10-25 16:40 ` Bryan O'Donoghue 2023-11-17 3:56 ` Sibi Sankar 2023-10-26 11:06 ` Konrad Dybcio 2023-10-27 8:21 ` Krzysztof Kozlowski 2 siblings, 1 reply; 14+ messages in thread From: Bryan O'Donoghue @ 2023-10-25 16:40 UTC (permalink / raw) To: Sibi Sankar, andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni On 25/10/2023 14:33, Sibi Sankar wrote: > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > Add support for the global clock controller found on SC8380XP > based devices. > > Co-developed-by: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- > drivers/clk/qcom/Kconfig | 10 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gcc-sc8380xp.c | 6812 +++++++++++++++++++++++++++++++ > 3 files changed, 6823 insertions(+) > create mode 100644 drivers/clk/qcom/gcc-sc8380xp.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index ad1acd9b7426..013b3a1ad551 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -515,6 +515,16 @@ config SC_GCC_8280XP > Say Y if you want to use peripheral devices such as UART, SPI, > I2C, USB, UFS, SDCC, etc. > > +config SC_GCC_8380XP > + tristate "SC8380XP Global Clock Controller" > + select QCOM_GDSC > + depends on COMMON_CLK_QCOM > + help > + Support for the global clock controller on Qualcomm Technologies, Inc > + SC8380XP devices. > + Say Y if you want to use peripheral devices such as UART, SPI, I2C, > + USB, UFS, SD/eMMC, PCIe, etc. > + > config SC_GPUCC_7180 > tristate "SC7180 Graphics Clock Controller" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 17edd73f9839..11b1f79e15c5 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -77,6 +77,7 @@ obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o > obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o > obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o > obj-$(CONFIG_SC_GCC_8280XP) += gcc-sc8280xp.o > +obj-$(CONFIG_SC_GCC_8380XP) += gcc-sc8380xp.o > obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o > obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o > obj-$(CONFIG_SC_GPUCC_8280XP) += gpucc-sc8280xp.o > diff --git a/drivers/clk/qcom/gcc-sc8380xp.c b/drivers/clk/qcom/gcc-sc8380xp.c > new file mode 100644 > index 000000000000..48c50f9421c8 > --- /dev/null > +++ b/drivers/clk/qcom/gcc-sc8380xp.c > @@ -0,0 +1,6812 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/regmap.h> > + > +#include <dt-bindings/clock/qcom,sc8380xp-gcc.h> > + > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" > +#include "clk-rcg.h" > +#include "clk-regmap.h" > +#include "clk-regmap-divider.h" > +#include "clk-regmap-mux.h" > +#include "clk-regmap-phy-mux.h" > +#include "gdsc.h" > +#include "reset.h" > + > +enum { > + DT_BI_TCXO, > + DT_SLEEP_CLK, > + DT_PCIE_3_PIPE, > + DT_PCIE_4_PIPE, > + DT_PCIE_5_PIPE, > + DT_PCIE_6A_PIPE, > + DT_PCIE_6B_PIPE, > + DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE, > + DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE, > + DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE, > +}; > + > +enum { > + P_BI_TCXO, > + P_GCC_GPLL0_OUT_EVEN, > + P_GCC_GPLL0_OUT_MAIN, > + P_GCC_GPLL4_OUT_MAIN, > + P_GCC_GPLL7_OUT_MAIN, > + P_GCC_GPLL8_OUT_MAIN, > + P_GCC_GPLL9_OUT_MAIN, > + P_SLEEP_CLK, > + P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, > + P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, > + P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, > +}; > + > +static struct clk_alpha_pll gcc_gpll0 = { > + .offset = 0x0, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .enable_reg = 0x52030, > + .enable_mask = BIT(0), > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_gpll0", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = { > + { 0x1, 2 }, > + { } > +}; > + > +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { > + .offset = 0x0, > + .post_div_shift = 10, > + .post_div_table = post_div_table_gcc_gpll0_out_even, > + .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), > + .width = 4, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_gpll0_out_even", > + .parent_hws = (const struct clk_hw*[]) { > + &gcc_gpll0.clkr.hw, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, > + }, > +}; > + > +static struct clk_alpha_pll gcc_gpll4 = { > + .offset = 0x4000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .enable_reg = 0x52030, > + .enable_mask = BIT(4), > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_gpll4", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, > + }, > + }, > +}; > + > +static struct clk_alpha_pll gcc_gpll7 = { > + .offset = 0x7000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .enable_reg = 0x52030, > + .enable_mask = BIT(7), > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_gpll7", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, > + }, > + }, > +}; > + > +static struct clk_alpha_pll gcc_gpll8 = { > + .offset = 0x8000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .enable_reg = 0x52030, > + .enable_mask = BIT(8), > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_gpll8", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, > + }, > + }, > +}; > + > +static struct clk_alpha_pll gcc_gpll9 = { > + .offset = 0x9000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > + .clkr = { > + .enable_reg = 0x52030, > + .enable_mask = BIT(9), > + .hw.init = &(const struct clk_init_data) { > + .name = "gcc_gpll9", > + .parent_data = &(const struct clk_parent_data) { > + .index = DT_BI_TCXO, > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, > + }, > + }, > +}; > + > +static const struct parent_map gcc_parent_map_0[] = { > + { P_BI_TCXO, 0 }, > + { P_GCC_GPLL0_OUT_MAIN, 1 }, > + { P_GCC_GPLL0_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_0[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &gcc_gpll0.clkr.hw }, > + { .hw = &gcc_gpll0_out_even.clkr.hw }, > +}; > + > +static const struct parent_map gcc_parent_map_1[] = { > + { P_BI_TCXO, 0 }, > + { P_SLEEP_CLK, 5 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_1[] = { > + { .index = DT_BI_TCXO }, > + { .index = DT_SLEEP_CLK }, > +}; > + > +static const struct parent_map gcc_parent_map_2[] = { > + { P_BI_TCXO, 0 }, > + { P_GCC_GPLL0_OUT_MAIN, 1 }, > + { P_SLEEP_CLK, 5 }, > + { P_GCC_GPLL0_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_2[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &gcc_gpll0.clkr.hw }, > + { .index = DT_SLEEP_CLK }, > + { .hw = &gcc_gpll0_out_even.clkr.hw }, > +}; > + > +static const struct parent_map gcc_parent_map_3[] = { > + { P_BI_TCXO, 0 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_3[] = { > + { .index = DT_BI_TCXO }, > +}; > + > +static const struct parent_map gcc_parent_map_4[] = { > + { P_BI_TCXO, 0 }, > + { P_GCC_GPLL0_OUT_MAIN, 1 }, > + { P_GCC_GPLL8_OUT_MAIN, 2 }, > + { P_GCC_GPLL0_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_4[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &gcc_gpll0.clkr.hw }, > + { .hw = &gcc_gpll8.clkr.hw }, > + { .hw = &gcc_gpll0_out_even.clkr.hw }, > +}; > + > +static const struct parent_map gcc_parent_map_5[] = { > + { P_BI_TCXO, 0 }, > + { P_GCC_GPLL0_OUT_MAIN, 1 }, > + { P_GCC_GPLL7_OUT_MAIN, 2 }, > + { P_SLEEP_CLK, 5 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_5[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &gcc_gpll0.clkr.hw }, > + { .hw = &gcc_gpll7.clkr.hw }, > + { .index = DT_SLEEP_CLK }, > +}; > + > +static const struct parent_map gcc_parent_map_6[] = { > + { P_BI_TCXO, 0 }, > + { P_GCC_GPLL0_OUT_MAIN, 1 }, > + { P_GCC_GPLL7_OUT_MAIN, 2 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_6[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &gcc_gpll0.clkr.hw }, > + { .hw = &gcc_gpll7.clkr.hw }, > +}; > + > +static const struct parent_map gcc_parent_map_7[] = { > + { P_BI_TCXO, 0 }, > + { P_GCC_GPLL0_OUT_MAIN, 1 }, > + { P_GCC_GPLL4_OUT_MAIN, 5 }, > + { P_GCC_GPLL0_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_7[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &gcc_gpll0.clkr.hw }, > + { .hw = &gcc_gpll4.clkr.hw }, > + { .hw = &gcc_gpll0_out_even.clkr.hw }, > +}; > + > +static const struct parent_map gcc_parent_map_8[] = { > + { P_BI_TCXO, 0 }, > + { P_GCC_GPLL0_OUT_MAIN, 1 }, > + { P_GCC_GPLL7_OUT_MAIN, 2 }, > + { P_GCC_GPLL0_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_8[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &gcc_gpll0.clkr.hw }, > + { .hw = &gcc_gpll7.clkr.hw }, > + { .hw = &gcc_gpll0_out_even.clkr.hw }, > +}; > + > +static const struct parent_map gcc_parent_map_9[] = { > + { P_BI_TCXO, 0 }, > + { P_GCC_GPLL0_OUT_MAIN, 1 }, > + { P_GCC_GPLL9_OUT_MAIN, 2 }, > + { P_GCC_GPLL4_OUT_MAIN, 5 }, > + { P_GCC_GPLL0_OUT_EVEN, 6 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_10[] = { > + { .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE }, > + { .index = DT_BI_TCXO }, > +}; > + > +static const struct parent_map gcc_parent_map_10[] = { > + { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, > + { P_BI_TCXO, 2 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_11[] = { > + { .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE }, > + { .index = DT_BI_TCXO }, > +}; > + > +static const struct parent_map gcc_parent_map_11[] = { > + { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, > + { P_BI_TCXO, 2 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_12[] = { > + { .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE }, > + { .index = DT_BI_TCXO }, > +}; > + > +static const struct parent_map gcc_parent_map_12[] = { > + { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, > + { P_BI_TCXO, 2 }, > +}; > + > +static const struct clk_parent_data gcc_parent_data_9[] = { > + { .index = DT_BI_TCXO }, > + { .hw = &gcc_gpll0.clkr.hw }, > + { .hw = &gcc_gpll9.clkr.hw }, > + { .hw = &gcc_gpll4.clkr.hw }, > + { .hw = &gcc_gpll0_out_even.clkr.hw }, > +}; > + > +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { > + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), > + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), > + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_gp1_clk_src = { > + .cmd_rcgr = 0x64004, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_2, > + .freq_tbl = ftbl_gcc_gp1_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_gp1_clk_src", > + .parent_data = gcc_parent_data_2, > + .num_parents = ARRAY_SIZE(gcc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_gp2_clk_src = { > + .cmd_rcgr = 0x65004, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_2, > + .freq_tbl = ftbl_gcc_gp1_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_gp2_clk_src", > + .parent_data = gcc_parent_data_2, > + .num_parents = ARRAY_SIZE(gcc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_gp3_clk_src = { > + .cmd_rcgr = 0x66004, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_2, > + .freq_tbl = ftbl_gcc_gp1_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_gp3_clk_src", > + .parent_data = gcc_parent_data_2, > + .num_parents = ARRAY_SIZE(gcc_parent_data_2), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { > + .cmd_rcgr = 0xa0180, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_1, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_0_aux_clk_src", > + .parent_data = gcc_parent_data_1, > + .num_parents = ARRAY_SIZE(gcc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { > + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { > + .cmd_rcgr = 0xa0054, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_0_phy_rchng_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { > + .cmd_rcgr = 0x2c180, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_1, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_1_aux_clk_src", > + .parent_data = gcc_parent_data_1, > + .num_parents = ARRAY_SIZE(gcc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { > + .cmd_rcgr = 0x2c054, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_1_phy_rchng_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { > + .cmd_rcgr = 0x13180, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_1, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_2_aux_clk_src", > + .parent_data = gcc_parent_data_1, > + .num_parents = ARRAY_SIZE(gcc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = { > + .cmd_rcgr = 0x13054, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_2_phy_rchng_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_3_aux_clk_src = { > + .cmd_rcgr = 0x5808c, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_1, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_3_aux_clk_src", > + .parent_data = gcc_parent_data_1, > + .num_parents = ARRAY_SIZE(gcc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = { > + .cmd_rcgr = 0x58070, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_3_phy_rchng_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_4_aux_clk_src = { > + .cmd_rcgr = 0x6b080, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_1, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_4_aux_clk_src", > + .parent_data = gcc_parent_data_1, > + .num_parents = ARRAY_SIZE(gcc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = { > + .cmd_rcgr = 0x6b064, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_4_phy_rchng_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_5_aux_clk_src = { > + .cmd_rcgr = 0x2f080, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_1, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_5_aux_clk_src", > + .parent_data = gcc_parent_data_1, > + .num_parents = ARRAY_SIZE(gcc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = { > + .cmd_rcgr = 0x2f064, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_5_phy_rchng_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = { > + .cmd_rcgr = 0x3108c, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_1, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_6a_aux_clk_src", > + .parent_data = gcc_parent_data_1, > + .num_parents = ARRAY_SIZE(gcc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = { > + .cmd_rcgr = 0x31070, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_6a_phy_rchng_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = { > + .cmd_rcgr = 0x8d08c, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_1, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_6b_aux_clk_src", > + .parent_data = gcc_parent_data_1, > + .num_parents = ARRAY_SIZE(gcc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = { > + .cmd_rcgr = 0x8d070, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_6b_phy_rchng_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = { > + .cmd_rcgr = 0xa400c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_3, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pcie_rscc_xo_clk_src", > + .parent_data = gcc_parent_data_3, > + .num_parents = ARRAY_SIZE(gcc_parent_data_3), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { > + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_pdm2_clk_src = { > + .cmd_rcgr = 0x33010, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pdm2_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_pdm2_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, Again difference to sc8280xp - should this be clk_rcg2_shared_ops to park ? > + }, > +}; > + > +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { > + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), > + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), > + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), > + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), > + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), > + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), > + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), > + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), > + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), > + { } > +}; > + > +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { > + .name = "gcc_qupv3_wrap0_s0_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, Shared on sc8280xp - should be shared on sc8380xp ? Same comment for all of the qupv3 .ops. > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { > + .cmd_rcgr = 0x42010, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { > + .name = "gcc_qupv3_wrap0_s1_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { > + .cmd_rcgr = 0x42148, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, > +}; > + > +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { > + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), > + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), > + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), > + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), > + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), > + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), > + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), > + F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), > + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), > + { } > +}; > + > +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { > + .name = "gcc_qupv3_wrap0_s2_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { > + .cmd_rcgr = 0x42288, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { > + .name = "gcc_qupv3_wrap0_s3_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { > + .cmd_rcgr = 0x423c8, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, > +}; > + > +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = { > + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), > + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), > + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), > + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), > + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), > + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), > + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), > + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), > + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), > + { } > +}; > + > +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { > + .name = "gcc_qupv3_wrap0_s4_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { > + .cmd_rcgr = 0x42500, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { > + .name = "gcc_qupv3_wrap0_s5_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { > + .cmd_rcgr = 0x42638, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { > + .name = "gcc_qupv3_wrap0_s6_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { > + .cmd_rcgr = 0x42770, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { > + .name = "gcc_qupv3_wrap0_s7_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { > + .cmd_rcgr = 0x428a8, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { > + .name = "gcc_qupv3_wrap1_s0_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { > + .cmd_rcgr = 0x18010, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { > + .name = "gcc_qupv3_wrap1_s1_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { > + .cmd_rcgr = 0x18148, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { > + .name = "gcc_qupv3_wrap1_s2_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { > + .cmd_rcgr = 0x18288, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { > + .name = "gcc_qupv3_wrap1_s3_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { > + .cmd_rcgr = 0x183c8, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { > + .name = "gcc_qupv3_wrap1_s4_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { > + .cmd_rcgr = 0x18500, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { > + .name = "gcc_qupv3_wrap1_s5_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { > + .cmd_rcgr = 0x18638, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { > + .name = "gcc_qupv3_wrap1_s6_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { > + .cmd_rcgr = 0x18770, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { > + .name = "gcc_qupv3_wrap1_s7_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { > + .cmd_rcgr = 0x188a8, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { > + .name = "gcc_qupv3_wrap2_s0_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { > + .cmd_rcgr = 0x1e010, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { > + .name = "gcc_qupv3_wrap2_s1_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { > + .cmd_rcgr = 0x1e148, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { > + .name = "gcc_qupv3_wrap2_s2_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { > + .cmd_rcgr = 0x1e288, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { > + .name = "gcc_qupv3_wrap2_s3_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { > + .cmd_rcgr = 0x1e3c8, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { > + .name = "gcc_qupv3_wrap2_s4_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { > + .cmd_rcgr = 0x1e500, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { > + .name = "gcc_qupv3_wrap2_s5_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { > + .cmd_rcgr = 0x1e638, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { > + .name = "gcc_qupv3_wrap2_s6_clk_src", > + .parent_data = gcc_parent_data_8, > + .num_parents = ARRAY_SIZE(gcc_parent_data_8), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { > + .cmd_rcgr = 0x1e770, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_8, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, > +}; > + > +static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { > + .name = "gcc_qupv3_wrap2_s7_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > +}; > + > +static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { > + .cmd_rcgr = 0x1e8a8, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, > + .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, > +}; > + > +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { > + F(400000, P_BI_TCXO, 12, 1, 4), > + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), > + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), > + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), > + F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { > + .cmd_rcgr = 0x14018, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = gcc_parent_map_9, > + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_sdcc2_apps_clk_src", > + .parent_data = gcc_parent_data_9, > + .num_parents = ARRAY_SIZE(gcc_parent_data_9), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_floor_ops, diff sc8280xp..sc8380xp Here you've used floor instead of shared ops, why is that ? > + }, > +}; > + > +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { > + F(400000, P_BI_TCXO, 12, 1, 4), > + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), > + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { > + .cmd_rcgr = 0x16018, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_sdcc4_apps_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_floor_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { > + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), > + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), > + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), > + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { > + .cmd_rcgr = 0x77030, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_ufs_phy_axi_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, This looks correct since you want to persist this clock in suspend presumably. > + }, > +}; > + > +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { > + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), > + F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), > + F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { > + .cmd_rcgr = 0x77080, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_7, > + .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_ufs_phy_ice_core_clk_src", > + .parent_data = gcc_parent_data_7, > + .num_parents = ARRAY_SIZE(gcc_parent_data_7), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { > + .cmd_rcgr = 0x770b4, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_3, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_ufs_phy_phy_aux_clk_src", > + .parent_data = gcc_parent_data_3, > + .num_parents = ARRAY_SIZE(gcc_parent_data_3), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, but then why not ufs_phy_ice_core and ufs_phy_phy_aux_clk > + }, > +}; > + > +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { > + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), > + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), > + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { > + .cmd_rcgr = 0x77098, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_ufs_phy_unipro_core_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, but back to the parked clock here. Shoudln't all of the UFS related clocks park in suspend ? > + }, > +}; > + > +static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { > + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), > + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_usb20_master_clk_src = { > + .cmd_rcgr = 0x2902c, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_usb20_master_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_usb20_master_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { > + .cmd_rcgr = 0x29158, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_usb20_mock_utmi_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = { > + F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), > + F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), > + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), > + F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_usb30_mp_master_clk_src = { > + .cmd_rcgr = 0x1702c, > + .mnd_width = 8, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_usb30_mp_master_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_shared_ops, > + }, > +}; > + > +static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { > + .cmd_rcgr = 0x17158, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > + .clkr.hw.init = &(const struct clk_init_data) { > + .name = "gcc_usb30_mp_mock_utmi_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, This is another discontinuinty with sc8280xp. Could you have a look through the sc8280xp gcc and do an aduit for clk_rcg2_shared_ops as against sc8380xp ? --- bod ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP 2023-10-25 16:40 ` [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP Bryan O'Donoghue @ 2023-11-17 3:56 ` Sibi Sankar 2023-11-17 8:13 ` Johan Hovold 2023-11-17 14:24 ` Bryan O'Donoghue 0 siblings, 2 replies; 14+ messages in thread From: Sibi Sankar @ 2023-11-17 3:56 UTC (permalink / raw) To: Bryan O'Donoghue, andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni Hey Bryan, Thanks for taking time to review the series. On 10/25/23 22:10, Bryan O'Donoghue wrote: > On 25/10/2023 14:33, Sibi Sankar wrote: >> From: Rajendra Nayak <quic_rjendra@quicinc.com> >> >> Add support for the global clock controller found on SC8380XP >> based devices. >> >> Co-developed-by: Abel Vesa <abel.vesa@linaro.org> >> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> >> Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> >> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> >> --- >> drivers/clk/qcom/Kconfig | 10 + >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/gcc-sc8380xp.c | 6812 +++++++++++++++++++++++++++++++ >> 3 files changed, 6823 insertions(+) >> create mode 100644 drivers/clk/qcom/gcc-sc8380xp.c >> >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >> index ad1acd9b7426..013b3a1ad551 100644 >> --- a/drivers/clk/qcom/Kconfig >> +++ b/drivers/clk/qcom/Kconfig >> @@ -515,6 +515,16 @@ config SC_GCC_8280XP >> Say Y if you want to use peripheral devices such as UART, SPI, >> I2C, USB, UFS, SDCC, etc. >> +config SC_GCC_8380XP >> + tristate "SC8380XP Global Clock Controller" >> + select QCOM_GDSC >> + depends on COMMON_CLK_QCOM >> + help >> + Support for the global clock controller on Qualcomm >> Technologies, Inc >> + SC8380XP devices. >> + Say Y if you want to use peripheral devices such as UART, SPI, >> I2C, >> + USB, UFS, SD/eMMC, PCIe, etc. >> + >> config SC_GPUCC_7180 >> tristate "SC7180 Graphics Clock Controller" >> depends on ARM64 || COMPILE_TEST >> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile >> index 17edd73f9839..11b1f79e15c5 100644 >> --- a/drivers/clk/qcom/Makefile >> +++ b/drivers/clk/qcom/Makefile >> @@ -77,6 +77,7 @@ obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o >> obj-$(CONFIG_SC_GCC_7280) += gcc-sc7280.o >> obj-$(CONFIG_SC_GCC_8180X) += gcc-sc8180x.o >> obj-$(CONFIG_SC_GCC_8280XP) += gcc-sc8280xp.o >> +obj-$(CONFIG_SC_GCC_8380XP) += gcc-sc8380xp.o >> obj-$(CONFIG_SC_GPUCC_7180) += gpucc-sc7180.o >> obj-$(CONFIG_SC_GPUCC_7280) += gpucc-sc7280.o >> obj-$(CONFIG_SC_GPUCC_8280XP) += gpucc-sc8280xp.o >> diff --git a/drivers/clk/qcom/gcc-sc8380xp.c >> b/drivers/clk/qcom/gcc-sc8380xp.c >> new file mode 100644 >> index 000000000000..48c50f9421c8 >> --- /dev/null >> +++ b/drivers/clk/qcom/gcc-sc8380xp.c >> @@ -0,0 +1,6812 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights >> reserved. >> + */ >> + >> +#include <linux/clk-provider.h> >> +#include <linux/module.h> >> +#include <linux/of_device.h> >> +#include <linux/regmap.h> >> + >> +#include <dt-bindings/clock/qcom,sc8380xp-gcc.h> >> + >> +#include "clk-alpha-pll.h" >> +#include "clk-branch.h" >> +#include "clk-rcg.h" >> +#include "clk-regmap.h" >> +#include "clk-regmap-divider.h" >> +#include "clk-regmap-mux.h" >> +#include "clk-regmap-phy-mux.h" >> +#include "gdsc.h" >> +#include "reset.h" >> + >> +enum { >> + DT_BI_TCXO, >> + DT_SLEEP_CLK, >> + DT_PCIE_3_PIPE, >> + DT_PCIE_4_PIPE, >> + DT_PCIE_5_PIPE, >> + DT_PCIE_6A_PIPE, >> + DT_PCIE_6B_PIPE, >> + DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE, >> + DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE, >> + DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE, >> +}; >> + >> +enum { >> + P_BI_TCXO, >> + P_GCC_GPLL0_OUT_EVEN, >> + P_GCC_GPLL0_OUT_MAIN, >> + P_GCC_GPLL4_OUT_MAIN, >> + P_GCC_GPLL7_OUT_MAIN, >> + P_GCC_GPLL8_OUT_MAIN, >> + P_GCC_GPLL9_OUT_MAIN, >> + P_SLEEP_CLK, >> + P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, >> + P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, >> + P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, >> +}; >> + >> +static struct clk_alpha_pll gcc_gpll0 = { >> + .offset = 0x0, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], >> + .clkr = { >> + .enable_reg = 0x52030, >> + .enable_mask = BIT(0), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_gpll0", >> + .parent_data = &(const struct clk_parent_data) { >> + .index = DT_BI_TCXO, >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, >> + }, >> + }, >> +}; >> + >> +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] >> = { >> + { 0x1, 2 }, >> + { } >> +}; >> + >> +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = { >> + .offset = 0x0, >> + .post_div_shift = 10, >> + .post_div_table = post_div_table_gcc_gpll0_out_even, >> + .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even), >> + .width = 4, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_gpll0_out_even", >> + .parent_hws = (const struct clk_hw*[]) { >> + &gcc_gpll0.clkr.hw, >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, >> + }, >> +}; >> + >> +static struct clk_alpha_pll gcc_gpll4 = { >> + .offset = 0x4000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], >> + .clkr = { >> + .enable_reg = 0x52030, >> + .enable_mask = BIT(4), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_gpll4", >> + .parent_data = &(const struct clk_parent_data) { >> + .index = DT_BI_TCXO, >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_alpha_pll gcc_gpll7 = { >> + .offset = 0x7000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], >> + .clkr = { >> + .enable_reg = 0x52030, >> + .enable_mask = BIT(7), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_gpll7", >> + .parent_data = &(const struct clk_parent_data) { >> + .index = DT_BI_TCXO, >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_alpha_pll gcc_gpll8 = { >> + .offset = 0x8000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], >> + .clkr = { >> + .enable_reg = 0x52030, >> + .enable_mask = BIT(8), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_gpll8", >> + .parent_data = &(const struct clk_parent_data) { >> + .index = DT_BI_TCXO, >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_alpha_pll gcc_gpll9 = { >> + .offset = 0x9000, >> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], >> + .clkr = { >> + .enable_reg = 0x52030, >> + .enable_mask = BIT(9), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "gcc_gpll9", >> + .parent_data = &(const struct clk_parent_data) { >> + .index = DT_BI_TCXO, >> + }, >> + .num_parents = 1, >> + .ops = &clk_alpha_pll_fixed_lucid_ole_ops, >> + }, >> + }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_0[] = { >> + { P_BI_TCXO, 0 }, >> + { P_GCC_GPLL0_OUT_MAIN, 1 }, >> + { P_GCC_GPLL0_OUT_EVEN, 6 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_0[] = { >> + { .index = DT_BI_TCXO }, >> + { .hw = &gcc_gpll0.clkr.hw }, >> + { .hw = &gcc_gpll0_out_even.clkr.hw }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_1[] = { >> + { P_BI_TCXO, 0 }, >> + { P_SLEEP_CLK, 5 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_1[] = { >> + { .index = DT_BI_TCXO }, >> + { .index = DT_SLEEP_CLK }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_2[] = { >> + { P_BI_TCXO, 0 }, >> + { P_GCC_GPLL0_OUT_MAIN, 1 }, >> + { P_SLEEP_CLK, 5 }, >> + { P_GCC_GPLL0_OUT_EVEN, 6 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_2[] = { >> + { .index = DT_BI_TCXO }, >> + { .hw = &gcc_gpll0.clkr.hw }, >> + { .index = DT_SLEEP_CLK }, >> + { .hw = &gcc_gpll0_out_even.clkr.hw }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_3[] = { >> + { P_BI_TCXO, 0 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_3[] = { >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_4[] = { >> + { P_BI_TCXO, 0 }, >> + { P_GCC_GPLL0_OUT_MAIN, 1 }, >> + { P_GCC_GPLL8_OUT_MAIN, 2 }, >> + { P_GCC_GPLL0_OUT_EVEN, 6 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_4[] = { >> + { .index = DT_BI_TCXO }, >> + { .hw = &gcc_gpll0.clkr.hw }, >> + { .hw = &gcc_gpll8.clkr.hw }, >> + { .hw = &gcc_gpll0_out_even.clkr.hw }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_5[] = { >> + { P_BI_TCXO, 0 }, >> + { P_GCC_GPLL0_OUT_MAIN, 1 }, >> + { P_GCC_GPLL7_OUT_MAIN, 2 }, >> + { P_SLEEP_CLK, 5 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_5[] = { >> + { .index = DT_BI_TCXO }, >> + { .hw = &gcc_gpll0.clkr.hw }, >> + { .hw = &gcc_gpll7.clkr.hw }, >> + { .index = DT_SLEEP_CLK }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_6[] = { >> + { P_BI_TCXO, 0 }, >> + { P_GCC_GPLL0_OUT_MAIN, 1 }, >> + { P_GCC_GPLL7_OUT_MAIN, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_6[] = { >> + { .index = DT_BI_TCXO }, >> + { .hw = &gcc_gpll0.clkr.hw }, >> + { .hw = &gcc_gpll7.clkr.hw }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_7[] = { >> + { P_BI_TCXO, 0 }, >> + { P_GCC_GPLL0_OUT_MAIN, 1 }, >> + { P_GCC_GPLL4_OUT_MAIN, 5 }, >> + { P_GCC_GPLL0_OUT_EVEN, 6 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_7[] = { >> + { .index = DT_BI_TCXO }, >> + { .hw = &gcc_gpll0.clkr.hw }, >> + { .hw = &gcc_gpll4.clkr.hw }, >> + { .hw = &gcc_gpll0_out_even.clkr.hw }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_8[] = { >> + { P_BI_TCXO, 0 }, >> + { P_GCC_GPLL0_OUT_MAIN, 1 }, >> + { P_GCC_GPLL7_OUT_MAIN, 2 }, >> + { P_GCC_GPLL0_OUT_EVEN, 6 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_8[] = { >> + { .index = DT_BI_TCXO }, >> + { .hw = &gcc_gpll0.clkr.hw }, >> + { .hw = &gcc_gpll7.clkr.hw }, >> + { .hw = &gcc_gpll0_out_even.clkr.hw }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_9[] = { >> + { P_BI_TCXO, 0 }, >> + { P_GCC_GPLL0_OUT_MAIN, 1 }, >> + { P_GCC_GPLL9_OUT_MAIN, 2 }, >> + { P_GCC_GPLL4_OUT_MAIN, 5 }, >> + { P_GCC_GPLL0_OUT_EVEN, 6 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_10[] = { >> + { .index = DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_10[] = { >> + { P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_11[] = { >> + { .index = DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_11[] = { >> + { P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_12[] = { >> + { .index = DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE }, >> + { .index = DT_BI_TCXO }, >> +}; >> + >> +static const struct parent_map gcc_parent_map_12[] = { >> + { P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK, 0 }, >> + { P_BI_TCXO, 2 }, >> +}; >> + >> +static const struct clk_parent_data gcc_parent_data_9[] = { >> + { .index = DT_BI_TCXO }, >> + { .hw = &gcc_gpll0.clkr.hw }, >> + { .hw = &gcc_gpll9.clkr.hw }, >> + { .hw = &gcc_gpll4.clkr.hw }, >> + { .hw = &gcc_gpll0_out_even.clkr.hw }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { >> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), >> + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), >> + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_gp1_clk_src = { >> + .cmd_rcgr = 0x64004, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_2, >> + .freq_tbl = ftbl_gcc_gp1_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_gp1_clk_src", >> + .parent_data = gcc_parent_data_2, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_2), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_gp2_clk_src = { >> + .cmd_rcgr = 0x65004, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_2, >> + .freq_tbl = ftbl_gcc_gp1_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_gp2_clk_src", >> + .parent_data = gcc_parent_data_2, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_2), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_gp3_clk_src = { >> + .cmd_rcgr = 0x66004, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_2, >> + .freq_tbl = ftbl_gcc_gp1_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_gp3_clk_src", >> + .parent_data = gcc_parent_data_2, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_2), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { >> + F(19200000, P_BI_TCXO, 1, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { >> + .cmd_rcgr = 0xa0180, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_1, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_0_aux_clk_src", >> + .parent_data = gcc_parent_data_1, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_1), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = { >> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = { >> + .cmd_rcgr = 0xa0054, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_0_phy_rchng_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { >> + .cmd_rcgr = 0x2c180, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_1, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_1_aux_clk_src", >> + .parent_data = gcc_parent_data_1, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_1), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = { >> + .cmd_rcgr = 0x2c054, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_1_phy_rchng_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { >> + .cmd_rcgr = 0x13180, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_1, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_2_aux_clk_src", >> + .parent_data = gcc_parent_data_1, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_1), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_2_phy_rchng_clk_src = { >> + .cmd_rcgr = 0x13054, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_2_phy_rchng_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_3_aux_clk_src = { >> + .cmd_rcgr = 0x5808c, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_1, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_3_aux_clk_src", >> + .parent_data = gcc_parent_data_1, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_1), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_3_phy_rchng_clk_src = { >> + .cmd_rcgr = 0x58070, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_3_phy_rchng_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_4_aux_clk_src = { >> + .cmd_rcgr = 0x6b080, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_1, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_4_aux_clk_src", >> + .parent_data = gcc_parent_data_1, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_1), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_4_phy_rchng_clk_src = { >> + .cmd_rcgr = 0x6b064, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_4_phy_rchng_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_5_aux_clk_src = { >> + .cmd_rcgr = 0x2f080, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_1, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_5_aux_clk_src", >> + .parent_data = gcc_parent_data_1, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_1), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_5_phy_rchng_clk_src = { >> + .cmd_rcgr = 0x2f064, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_5_phy_rchng_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_6a_aux_clk_src = { >> + .cmd_rcgr = 0x3108c, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_1, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_6a_aux_clk_src", >> + .parent_data = gcc_parent_data_1, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_1), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_6a_phy_rchng_clk_src = { >> + .cmd_rcgr = 0x31070, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_6a_phy_rchng_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_6b_aux_clk_src = { >> + .cmd_rcgr = 0x8d08c, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_1, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_6b_aux_clk_src", >> + .parent_data = gcc_parent_data_1, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_1), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_6b_phy_rchng_clk_src = { >> + .cmd_rcgr = 0x8d070, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_6b_phy_rchng_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_pcie_rscc_xo_clk_src = { >> + .cmd_rcgr = 0xa400c, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_3, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pcie_rscc_xo_clk_src", >> + .parent_data = gcc_parent_data_3, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_3), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { >> + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_pdm2_clk_src = { >> + .cmd_rcgr = 0x33010, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pdm2_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_pdm2_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, > > Again difference to sc8280xp - should this be clk_rcg2_shared_ops to park ? > >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { >> + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), >> + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), >> + F(19200000, P_BI_TCXO, 1, 0, 0), >> + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), >> + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), >> + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), >> + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), >> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), >> + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), >> + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), >> + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), >> + { } >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { >> + .name = "gcc_qupv3_wrap0_s0_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, > > Shared on sc8280xp - should be shared on sc8380xp ? Same comment for all > of the qupv3 .ops. > >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { >> + .cmd_rcgr = 0x42010, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { >> + .name = "gcc_qupv3_wrap0_s1_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { >> + .cmd_rcgr = 0x42148, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { >> + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), >> + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), >> + F(19200000, P_BI_TCXO, 1, 0, 0), >> + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), >> + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), >> + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), >> + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), >> + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), >> + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), >> + F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0), >> + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), >> + { } >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { >> + .name = "gcc_qupv3_wrap0_s2_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { >> + .cmd_rcgr = 0x42288, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { >> + .name = "gcc_qupv3_wrap0_s3_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { >> + .cmd_rcgr = 0x423c8, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s4_clk_src[] = { >> + F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625), >> + F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625), >> + F(19200000, P_BI_TCXO, 1, 0, 0), >> + F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625), >> + F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75), >> + F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25), >> + F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75), >> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), >> + F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15), >> + F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25), >> + F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0), >> + { } >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { >> + .name = "gcc_qupv3_wrap0_s4_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { >> + .cmd_rcgr = 0x42500, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { >> + .name = "gcc_qupv3_wrap0_s5_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { >> + .cmd_rcgr = 0x42638, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { >> + .name = "gcc_qupv3_wrap0_s6_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { >> + .cmd_rcgr = 0x42770, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { >> + .name = "gcc_qupv3_wrap0_s7_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { >> + .cmd_rcgr = 0x428a8, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { >> + .name = "gcc_qupv3_wrap1_s0_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { >> + .cmd_rcgr = 0x18010, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { >> + .name = "gcc_qupv3_wrap1_s1_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { >> + .cmd_rcgr = 0x18148, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { >> + .name = "gcc_qupv3_wrap1_s2_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { >> + .cmd_rcgr = 0x18288, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { >> + .name = "gcc_qupv3_wrap1_s3_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { >> + .cmd_rcgr = 0x183c8, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { >> + .name = "gcc_qupv3_wrap1_s4_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { >> + .cmd_rcgr = 0x18500, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { >> + .name = "gcc_qupv3_wrap1_s5_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { >> + .cmd_rcgr = 0x18638, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { >> + .name = "gcc_qupv3_wrap1_s6_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { >> + .cmd_rcgr = 0x18770, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { >> + .name = "gcc_qupv3_wrap1_s7_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { >> + .cmd_rcgr = 0x188a8, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { >> + .name = "gcc_qupv3_wrap2_s0_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { >> + .cmd_rcgr = 0x1e010, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { >> + .name = "gcc_qupv3_wrap2_s1_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { >> + .cmd_rcgr = 0x1e148, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { >> + .name = "gcc_qupv3_wrap2_s2_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { >> + .cmd_rcgr = 0x1e288, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { >> + .name = "gcc_qupv3_wrap2_s3_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { >> + .cmd_rcgr = 0x1e3c8, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { >> + .name = "gcc_qupv3_wrap2_s4_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { >> + .cmd_rcgr = 0x1e500, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { >> + .name = "gcc_qupv3_wrap2_s5_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { >> + .cmd_rcgr = 0x1e638, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { >> + .name = "gcc_qupv3_wrap2_s6_clk_src", >> + .parent_data = gcc_parent_data_8, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_8), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { >> + .cmd_rcgr = 0x1e770, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_8, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init, >> +}; >> + >> +static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { >> + .name = "gcc_qupv3_wrap2_s7_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> +}; >> + >> +static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { >> + .cmd_rcgr = 0x1e8a8, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_qupv3_wrap0_s4_clk_src, >> + .clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { >> + F(400000, P_BI_TCXO, 12, 1, 4), >> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), >> + F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0), >> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), >> + F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { >> + .cmd_rcgr = 0x14018, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_9, >> + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_sdcc2_apps_clk_src", >> + .parent_data = gcc_parent_data_9, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_9), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_floor_ops, > > diff sc8280xp..sc8380xp > > Here you've used floor instead of shared ops, why is that ? We seem to use floor ops for sdcc clks on all other QC SoCs and sc8280xp seems to be the exception here. So I'll continue to use floor ops for sdcc. > >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { >> + F(400000, P_BI_TCXO, 12, 1, 4), >> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), >> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { >> + .cmd_rcgr = 0x16018, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_sdcc4_apps_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_floor_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { >> + F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0), >> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), >> + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), >> + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { >> + .cmd_rcgr = 0x77030, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_ufs_phy_axi_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, > > This looks correct since you want to persist this clock in suspend > presumably. > >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { >> + F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0), >> + F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0), >> + F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { >> + .cmd_rcgr = 0x77080, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_7, >> + .freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_ufs_phy_ice_core_clk_src", >> + .parent_data = gcc_parent_data_7, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_7), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { >> + .cmd_rcgr = 0x770b4, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_3, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_ufs_phy_phy_aux_clk_src", >> + .parent_data = gcc_parent_data_3, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_3), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, > > but then why not ufs_phy_ice_core and ufs_phy_phy_aux_clk > >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { >> + F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0), >> + F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0), >> + F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { >> + .cmd_rcgr = 0x77098, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_ufs_phy_unipro_core_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_ufs_phy_unipro_core_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, > > but back to the parked clock here. > > Shoudln't all of the UFS related clocks park in suspend ? > >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = { >> + F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0), >> + F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_usb20_master_clk_src = { >> + .cmd_rcgr = 0x2902c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_usb20_master_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_usb20_master_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_usb20_mock_utmi_clk_src = { >> + .cmd_rcgr = 0x29158, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_usb20_mock_utmi_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_gcc_usb30_mp_master_clk_src[] = { >> + F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0), >> + F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0), >> + F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0), >> + F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_usb30_mp_master_clk_src = { >> + .cmd_rcgr = 0x1702c, >> + .mnd_width = 8, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_usb30_mp_master_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_usb30_mp_master_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_shared_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { >> + .cmd_rcgr = 0x17158, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data) { >> + .name = "gcc_usb30_mp_mock_utmi_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, > > This is another discontinuinty with sc8280xp. > > Could you have a look through the sc8280xp gcc and do an aduit for > clk_rcg2_shared_ops as against sc8380xp ? ack, will do a quick audit before the re-spin. > > --- > bod ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP 2023-11-17 3:56 ` Sibi Sankar @ 2023-11-17 8:13 ` Johan Hovold 2023-11-17 14:24 ` Bryan O'Donoghue 1 sibling, 0 replies; 14+ messages in thread From: Johan Hovold @ 2023-11-17 8:13 UTC (permalink / raw) To: Sibi Sankar Cc: Bryan O'Donoghue, andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt, agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni On Fri, Nov 17, 2023 at 09:26:18AM +0530, Sibi Sankar wrote: > On 10/25/23 22:10, Bryan O'Donoghue wrote: > > On 25/10/2023 14:33, Sibi Sankar wrote: > >> +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { > >> + .cmd_rcgr = 0x14018, > >> + .mnd_width = 8, > >> + .hid_width = 5, > >> + .parent_map = gcc_parent_map_9, > >> + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, > >> + .clkr.hw.init = &(const struct clk_init_data) { > >> + .name = "gcc_sdcc2_apps_clk_src", > >> + .parent_data = gcc_parent_data_9, > >> + .num_parents = ARRAY_SIZE(gcc_parent_data_9), > >> + .flags = CLK_SET_RATE_PARENT, > >> + .ops = &clk_rcg2_floor_ops, > > > > diff sc8280xp..sc8380xp > > > > Here you've used floor instead of shared ops, why is that ? > > We seem to use floor ops for sdcc clks on all other QC SoCs and > sc8280xp seems to be the exception here. So I'll continue to use floor > ops for sdcc. > >> +static struct clk_rcg2 gcc_usb30_mp_mock_utmi_clk_src = { > >> + .cmd_rcgr = 0x17158, > >> + .mnd_width = 0, > >> + .hid_width = 5, > >> + .parent_map = gcc_parent_map_0, > >> + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, > >> + .clkr.hw.init = &(const struct clk_init_data) { > >> + .name = "gcc_usb30_mp_mock_utmi_clk_src", > >> + .parent_data = gcc_parent_data_0, > >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > >> + .flags = CLK_SET_RATE_PARENT, > >> + .ops = &clk_rcg2_ops, > > > > This is another discontinuinty with sc8280xp. > > > > Could you have a look through the sc8280xp gcc and do an aduit for > > clk_rcg2_shared_ops as against sc8380xp ? > > ack, will do a quick audit before the re-spin. Please trim unnecessary context from your replies. You quoted some 1400 lines of irrelevant clock structs when all you needed was something like the above. Not trimming replies makes it a pain to read your mails and to revisit threads like this one, for example, in the lore web archives. Johan ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP 2023-11-17 3:56 ` Sibi Sankar 2023-11-17 8:13 ` Johan Hovold @ 2023-11-17 14:24 ` Bryan O'Donoghue 1 sibling, 0 replies; 14+ messages in thread From: Bryan O'Donoghue @ 2023-11-17 14:24 UTC (permalink / raw) To: Sibi Sankar, andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni On 17/11/2023 03:56, Sibi Sankar wrote: >> >> This is another discontinuinty with sc8280xp. >> >> Could you have a look through the sc8280xp gcc and do an aduit for >> clk_rcg2_shared_ops as against sc8380xp ? > > ack, will do a quick audit before the re-spin. A best guess will do, we will "shake out the bugs" through suspend/resume real use cases anyway but, worth a quick pass since you are doing a v2 for the SoC name. --- bod ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP [not found] ` <20231025133320.4720-3-quic_sibis@quicinc.com> 2023-10-25 16:40 ` [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP Bryan O'Donoghue @ 2023-10-26 11:06 ` Konrad Dybcio 2023-10-27 8:21 ` Krzysztof Kozlowski 2 siblings, 0 replies; 14+ messages in thread From: Konrad Dybcio @ 2023-10-26 11:06 UTC (permalink / raw) To: Sibi Sankar, andersson, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni On 10/25/23 15:33, Sibi Sankar wrote: > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > Add support for the global clock controller found on SC8380XP > based devices. > > Co-developed-by: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- [...] > +static int gcc_sc8380xp_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + int ret; > + > + regmap = qcom_cc_map(pdev, &gcc_sc8380xp_desc); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, > + ARRAY_SIZE(gcc_dfs_clocks)); > + if (ret) > + return ret; > + > + /* > + * Keep the critical clock always-On > + * gcc_camera_ahb_clk, gcc_camera_xo_clk, gcc_disp_ahb_clk, > + * gcc_disp_xo_clk, gcc_gpu_cfg_ahb_clk, gcc_video_ahb_clk, > + * gcc_video_xo_clk > + */ > + regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); Please inline the clock names, like so: regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); /* gcc_camera_ahb_clk */ LGTM otherwise Konrad ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP [not found] ` <20231025133320.4720-3-quic_sibis@quicinc.com> 2023-10-25 16:40 ` [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP Bryan O'Donoghue 2023-10-26 11:06 ` Konrad Dybcio @ 2023-10-27 8:21 ` Krzysztof Kozlowski 2 siblings, 0 replies; 14+ messages in thread From: Krzysztof Kozlowski @ 2023-10-27 8:21 UTC (permalink / raw) To: Sibi Sankar, andersson, konrad.dybcio, mturquette, sboyd, robh+dt, krzysztof.kozlowski+dt Cc: agross, conor+dt, quic_tdas, quic_rjendra, linux-arm-msm, linux-clk, devicetree, linux-kernel, neil.armstrong, abel.vesa, quic_tsoni On 25/10/2023 15:33, Sibi Sankar wrote: > From: Rajendra Nayak <quic_rjendra@quicinc.com> > > Add support for the global clock controller found on SC8380XP > based devices. > > Co-developed-by: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com> > Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com> > --- > drivers/clk/qcom/Kconfig | 10 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gcc-sc8380xp.c | 6812 +++++++++++++++++++++++++++++++ > 3 files changed, 6823 insertions(+) > create mode 100644 drivers/clk/qcom/gcc-sc8380xp.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index ad1acd9b7426..013b3a1ad551 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -515,6 +515,16 @@ config SC_GCC_8280XP > Say Y if you want to use peripheral devices such as UART, SPI, > I2C, USB, UFS, SDCC, etc. > > +config SC_GCC_8380XP > + tristate "SC8380XP Global Clock Controller" > + select QCOM_GDSC > + depends on COMMON_CLK_QCOM Please stgart any new work starting from some driver in linux-next. You would not make the same mistakes we fixed recently. depends on ARM64 || COMPILE_TEST Best regards, Krzysztof ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-11-17 14:24 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
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2023-10-25 13:33 [PATCH 0/4] clk: qcom: Introduce clocks drivers for SC8380XP Sibi Sankar
2023-10-25 13:33 ` [PATCH 1/4] dt-bindings: clock: qcom: Add SC8380XP GCC clocks Sibi Sankar
2023-10-27 8:20 ` Krzysztof Kozlowski
2023-10-25 13:33 ` [PATCH 3/4] dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for SC8380XP Sibi Sankar
2023-10-27 8:20 ` Krzysztof Kozlowski
2023-10-25 13:33 ` [PATCH 4/4] clk: qcom: rpmh: Add support for SC8380XP rpmh clocks Sibi Sankar
2023-10-25 20:38 ` Bryan O'Donoghue
2023-10-26 11:07 ` Konrad Dybcio
[not found] ` <20231025133320.4720-3-quic_sibis@quicinc.com>
2023-10-25 16:40 ` [PATCH 2/4] clk: qcom: Add Global Clock controller (GCC) driver for SC8380XP Bryan O'Donoghue
2023-11-17 3:56 ` Sibi Sankar
2023-11-17 8:13 ` Johan Hovold
2023-11-17 14:24 ` Bryan O'Donoghue
2023-10-26 11:06 ` Konrad Dybcio
2023-10-27 8:21 ` Krzysztof Kozlowski
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