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Thu, 20 Jun 2024 22:05:24 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45KM5MoV023845 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Jun 2024 22:05:22 GMT Received: from [10.110.82.141] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 20 Jun 2024 15:05:18 -0700 Message-ID: <8dd4a43e-d83c-1f36-21ff-61e13ff751e7@quicinc.com> Date: Thu, 20 Jun 2024 15:05:16 -0700 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v5 5/9] drm/msm/hdmi: turn mode_set into atomic_enable Content-Language: en-US To: Dmitry Baryshkov CC: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Clark , Sean Paul , Marijn Suijten , , , , References: <20240607-bridge-hdmi-connector-v5-0-ab384e6021af@linaro.org> <20240607-bridge-hdmi-connector-v5-5-ab384e6021af@linaro.org> <6d416e1a-1069-8355-e9f3-d2732df081a3@quicinc.com> From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 46wqhs0be5KKmtJK3ZXUKY61neLK-sdU X-Proofpoint-ORIG-GUID: 46wqhs0be5KKmtJK3ZXUKY61neLK-sdU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-20_10,2024-06-20_04,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 phishscore=0 clxscore=1015 malwarescore=0 spamscore=0 suspectscore=0 bulkscore=0 mlxscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406200162 On 6/20/2024 2:24 PM, Dmitry Baryshkov wrote: > On Thu, Jun 20, 2024 at 01:49:33PM GMT, Abhinav Kumar wrote: >> >> >> On 6/20/2024 1:32 PM, Dmitry Baryshkov wrote: >>> On Thu, Jun 20, 2024 at 01:27:15PM GMT, Abhinav Kumar wrote: >>>> >>>> >>>> On 6/7/2024 6:23 AM, Dmitry Baryshkov wrote: >>>>> The mode_set callback is deprecated, it doesn't get the >>>>> drm_bridge_state, just mode-related argumetns. Turn it into the >>>>> atomic_enable callback as suggested by the documentation. >>>>> >>>> >>>> mode_set is deprecated but atomic_mode_set is not. >>> >>> There is no atomic_mode_set() in drm_bridge_funcs. Also: >>> >> >> Please excuse me. I thought since encoder has atomic_mode_set(), bridge has >> one too. >> >>> * This is deprecated, do not use! >>> * New drivers shall set their mode in the >>> * &drm_bridge_funcs.atomic_enable operation. >>> >> >> Yes I saw this note but it also says "new drivers" and not really enforcing >> migrating existing ones which are using modeset to atomic_enable. > > Well, deprecated functions are supposed to be migrated. > Along with rest of the pieces of the driver :) >> My concern is that today the timing engine setup happens in encoder's >> enable() and the hdmi's timing is programmed in mode_set(). >> >> Ideally, we should program hdmi's timing registers first before the >> encoder's timing. >> >> Although timing engine is not enabled yet, till post_kickoff, this is >> changing the sequence. >> >> If this really required for rest of this series? > > No, it was just worth doing it as I was doing conversion to atomic_* > anyway. I can delay this patch for now. > > Two questions: > > 1) Are you sure regarding the HDMI timing registers vs INTF order? I > observe the underrun issues while changing modes on db820c. > Yes this is the order I see in the docs: 1) setup HDMI PHY and PLL 2) setup HDMI video path correctly (HDMI timing registers) 3) setup timing generator to match the HDMI video in (2) 4) Enable timing engine This change is mixing up the order of (2) and (3). > 2) What should be the order between programming of the HDMI timing > engine and HDMI PHY? > Mentioned above. > What would be your opinion on moving HDMI timing programming to > atomic_pre_enable? (the exact place depends on the answer on the second > question). > So -> bridge->pre_enable() : Do HDMI timing programming -> encoder->atomic_enable() : Do timing engine programming -> post_kickoff() does timing engine enable This matches the steps I wrote above. Hence this is fine from my PoV. >> >>>> >>>> I would rather use atomic_mode_set because moving to atomic_enable() would >>>> be incorrect. >>>> >>>> That would be called after encoder's enable and hence changes the sequence. >>>> That was not the intention of this patch. >>>> >>>> NAK. >>>> >>>>> Acked-by: Maxime Ripard >>>>> Signed-off-by: Dmitry Baryshkov >>>>> --- >>>>> drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 33 ++++++++++++++++++++++++++------- >>>>> 1 file changed, 26 insertions(+), 7 deletions(-) >>> >>> >