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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-382861ef4ccsm45978701fa.23.2026.01.02.04.40.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 Jan 2026 04:40:25 -0800 (PST) Message-ID: <91d2e5f7-7d93-4909-9ed2-6b19abf0b448@oss.qualcomm.com> Date: Fri, 2 Jan 2026 13:40:22 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] pinctrl: qcom: glymur: Add Mahua TLMM support To: Gopikrishna Garmidi , Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Pankaj Patil , Sibi Sankar , Manivannan Sadhasivam Cc: Bjorn Andersson , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260102-pinctrl-qcom-mahua-tlmm-v1-0-0edd71af08b2@oss.qualcomm.com> <20260102-pinctrl-qcom-mahua-tlmm-v1-2-0edd71af08b2@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260102-pinctrl-qcom-mahua-tlmm-v1-2-0edd71af08b2@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: oELR9Lu94OyQoitSNJHKrxnHzVQ0EOlP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTAyMDExMiBTYWx0ZWRfX4rMUACDQOtuf Ss77zJK6Nnf4QMwh+f6eOvMXFLh6PuVpykSiOKuJxZuZGKKxGhqApIFMYiNzcYNtbsShbzdVGE0 6CdU7PFDGEnhwuVaE1sWYRA4doG7+MwU6PtOrqQNYx0hXCLAd58CarGVJuHmB+NfK/FgBbXAu3V 8Z5Rk7/USPkNTwZBzPhvCClxm3wu11pVzHf4N43t15JVOk9icnT9x914UslfzRaQkc2nAI/DkHa Mu+aY0wqYVzpBHYJ+QBik2kwHxbEZYmXo92fnUuzwGB+jUFrzQl2X99IKOLROahfo/XbAWWxhHu KZ5o1ctD332fMq/vI6ZOreVeaJVgS7zdf3kam0eLi99OzhluLpWLB/HBgNPY+jKTmZk89nJqIES evEjvDdOC86dgQu6O/Gdsq0yG9nAi2nMEMjmFMtMGvHZ1QRekdu7c6wae9jq0w+SMPDvdO8LdAe blWe9CT63vwaSxH2tpg== X-Authority-Analysis: v=2.4 cv=I5pohdgg c=1 sm=1 tr=0 ts=6957bcbc cx=c_pps a=oc9J++0uMp73DTRD5QyR2A==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=9J1-as2qgA27kOtx8oUA:9 a=QEXdDO2ut3YA:10 a=iYH6xdkBrDN1Jqds4HTS:22 X-Proofpoint-GUID: oELR9Lu94OyQoitSNJHKrxnHzVQ0EOlP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-02_01,2025-12-31_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 malwarescore=0 spamscore=0 impostorscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601020112 On 1/2/26 12:07 PM, Gopikrishna Garmidi wrote: > Introduce support for the Mahua TLMM (Top Level Mode Multiplexer) > in the pinctrl-glymur driver. Mahua shares the same pin configuration > as Glymur but requires a different PDC wake IRQ mapping. > > Changes include: > - Add mahua_pdc_map[] with Mahua-specific GPIO to PDC IRQ mappings > - Define mahua_tlmm msm_pinctrl_soc_data structure > - Update device match table to include "qcom,mahua-tlmm" compatible > - Modify probe function to use of_device_get_match_data() for dynamic > SoC-specific data selection > > Signed-off-by: Gopikrishna Garmidi > --- > drivers/pinctrl/qcom/pinctrl-glymur.c | 43 ++++++++++++++++++++++++++++++++--- > 1 file changed, 40 insertions(+), 3 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-glymur.c b/drivers/pinctrl/qcom/pinctrl-glymur.c > index 335005084b6b..bf56a064d09c 100644 > --- a/drivers/pinctrl/qcom/pinctrl-glymur.c > +++ b/drivers/pinctrl/qcom/pinctrl-glymur.c > @@ -1729,6 +1729,25 @@ static const struct msm_gpio_wakeirq_map glymur_pdc_map[] = { > { 232, 206 }, { 234, 172 }, { 235, 173 }, { 242, 158 }, { 244, 156 }, > }; > > +static const struct msm_gpio_wakeirq_map mahua_pdc_map[] = { > + { 0, 116 }, { 2, 114 }, { 3, 115 }, { 4, 175 }, { 5, 176 }, > + { 7, 111 }, { 11, 129 }, { 13, 130 }, { 15, 112 }, { 19, 113 }, > + { 23, 187 }, { 27, 188 }, { 28, 121 }, { 29, 122 }, { 30, 136 }, > + { 31, 203 }, { 32, 189 }, { 34, 174 }, { 35, 190 }, { 36, 191 }, > + { 39, 124 }, { 43, 192 }, { 47, 193 }, { 51, 123 }, { 53, 133 }, > + { 55, 125 }, { 59, 131 }, { 64, 134 }, { 65, 150 }, { 66, 186 }, > + { 67, 132 }, { 68, 195 }, { 71, 135 }, { 75, 196 }, { 79, 197 }, > + { 83, 198 }, { 84, 181 }, { 85, 199 }, { 87, 200 }, { 91, 201 }, > + { 92, 182 }, { 93, 183 }, { 94, 184 }, { 95, 185 }, { 98, 202 }, > + { 105, 157 }, { 113, 128 }, { 121, 117 }, { 123, 118 }, { 125, 119 }, > + { 129, 120 }, { 131, 126 }, { 132, 160 }, { 133, 194 }, { 134, 127 }, > + { 141, 137 }, { 144, 138 }, { 145, 139 }, { 147, 140 }, { 148, 141 }, > + { 150, 146 }, { 151, 147 }, { 153, 148 }, { 154, 144 }, { 155, 159 }, > + { 156, 149 }, { 157, 151 }, { 163, 142 }, { 172, 143 }, { 181, 145 }, > + { 193, 161 }, { 196, 152 }, { 203, 177 }, { 208, 178 }, { 215, 162 }, > + { 217, 153 }, { 220, 154 }, { 221, 155 }, { 228, 179 }, { 230, 180 }, > + { 232, 206 }, { 234, 172 }, { 235, 173 }, { 242, 158 }, { 244, 156 }, Over the "common" base, Glymur has GPIO143 (PCIE3a_RST) and Mahua has GPIO155 (PCIE3b_RST). Both SoCs GPIO maps seem to contain both, but Mahua has a _unused suffix for the missing 143, which makes sense given the bus isn't bifurcated there. The _RST (PERST#) pin is driven by the SoC so I don't think it's useful to have it as a wakeup source, unless someone decides to connect something that's not PCIe to it (+Mani) Perhaps we could unify these maps? Konrad