From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
To: Konrad Dybcio <konrad.dybcio@linaro.org>, <bhelgaas@google.com>,
<lpieralisi@kernel.org>, <kw@linux.com>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<andersson@kernel.org>, <manivannan.sadhasivam@linaro.org>,
<linux-arm-msm@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: devi priya <quic_devipriy@quicinc.com>
Subject: Re: [PATCH V6 2/4] arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes
Date: Thu, 18 Jul 2024 12:09:39 +0530 [thread overview]
Message-ID: <927af089-ecd0-4175-ab13-e6086aac9ce3@quicinc.com> (raw)
In-Reply-To: <dbd172e0-d7c6-4ecc-b8cd-1329a4b03374@linaro.org>
On 7/16/2024 5:33 PM, Konrad Dybcio wrote:
> On 16.07.2024 11:23 AM, Sricharan R wrote:
>> From: devi priya <quic_devipriy@quicinc.com>
>>
>> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
>> found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
>> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
>> ---
> [...]
>
>> +
>> + ranges = <0x01000000 0x0 0x00000000 0x10200000 0x0 0x100000>, /* I/O */
>> + <0x02000000 0x0 0x10300000 0x10300000 0x0 0x7d00000>; /* MEM */
> Drop these comments, please
ok
>> +
>> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>> +
> Inconsistent newline
ok, will fix
>> + interrupt-names = "msi0",
>> + "msi1",
>> + "msi2",
>> + "msi3",
>> + "msi4",
>> + "msi5",
>> + "msi6",
>> + "msi7";
>> +
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0x7>;
>> + interrupt-map = <0 0 0 1 &intc 0 0 35 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
>> + <0 0 0 2 &intc 0 0 49 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
>> + <0 0 0 3 &intc 0 0 84 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
>> + <0 0 0 4 &intc 0 0 85 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> Drop these comments, please
>
> (all these comments apply to all the similar nodes)
ok
> [...]
>
>> +
>> + pcie3: pcie@18000000 {
>> + compatible = "qcom,pcie-ipq9574";
>> + reg = <0x18000000 0xf1d>,
>> + <0x18000f20 0xa8>,
>> + <0x18001000 0x1000>,
>> + <0x000f0000 0x4000>,
>> + <0x18100000 0x1000>;
>> + reg-names = "dbi", "elbi", "atu", "parf", "config";
>> + device_type = "pci";
>> + linux,pci-domain = <4>;
> Any reason the PCI domain for PCIeN is N+1? You can start at 0
ok, will fix
Regards,
Sricharan
next prev parent reply other threads:[~2024-07-18 6:39 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-16 9:23 [PATCH V6 0/4] Add PCIe support for IPQ9574 Sricharan R
2024-07-16 9:23 ` [PATCH V6 1/4] dt-bindings: PCI: qcom: Document the IPQ9574 PCIe controller Sricharan R
2024-07-16 19:42 ` Krzysztof Kozlowski
2024-07-18 6:40 ` Sricharan Ramabadhran
2024-07-17 8:40 ` Manivannan Sadhasivam
2024-07-16 9:23 ` [PATCH V6 2/4] arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes Sricharan R
2024-07-16 12:03 ` Konrad Dybcio
2024-07-18 6:39 ` Sricharan Ramabadhran [this message]
2024-07-16 9:23 ` [PATCH V6 3/4] arm64: dts: qcom: ipq9574: Enable PCIe PHYs and controllers Sricharan R
2024-07-16 12:03 ` Konrad Dybcio
2024-07-18 6:40 ` Sricharan Ramabadhran
2024-07-16 9:23 ` [PATCH V6 4/4] PCI: qcom: Add support for IPQ9574 Sricharan R
2024-07-17 8:38 ` Manivannan Sadhasivam
2024-07-18 6:43 ` Sricharan Ramabadhran
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