From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 562DFC388F9 for ; Mon, 2 Nov 2020 18:32:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1445822280 for ; Mon, 2 Nov 2020 18:32:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726351AbgKBScV (ORCPT ); Mon, 2 Nov 2020 13:32:21 -0500 Received: from foss.arm.com ([217.140.110.172]:36062 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725789AbgKBScV (ORCPT ); Mon, 2 Nov 2020 13:32:21 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D34FD139F; Mon, 2 Nov 2020 10:32:20 -0800 (PST) Received: from [10.57.54.223] (unknown [10.57.54.223]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DEF683F719; Mon, 2 Nov 2020 10:32:18 -0800 (PST) Subject: Re: [PATCH v18 3/4] dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU From: Robin Murphy To: Jordan Crouse , linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org, Will Deacon , Rob Herring , Rob Clark , Bjorn Andersson , Joerg Roedel , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20201102171416.654337-1-jcrouse@codeaurora.org> <20201102171416.654337-4-jcrouse@codeaurora.org> <77278507-a6be-8517-6f76-02a0ff588e39@arm.com> Message-ID: <9409941f-366e-4dca-f49b-48eeff1ea248@arm.com> Date: Mon, 2 Nov 2020 18:32:17 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <77278507-a6be-8517-6f76-02a0ff588e39@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2020-11-02 18:22, Robin Murphy wrote: > On 2020-11-02 17:14, Jordan Crouse wrote: >> Every Qcom Adreno GPU has an embedded SMMU for its own use. These >> devices depend on unique features such as split pagetables, >> different stall/halt requirements and other settings. Identify them >> with a compatible string so that they can be identified in the >> arm-smmu implementation specific code. >> >> Signed-off-by: Jordan Crouse >> Reviewed-by: Rob Herring >> Signed-off-by: Rob Clark >> Reviewed-by: Bjorn Andersson >> --- >> >>   Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++++++-- >>   1 file changed, 7 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> index 503160a7b9a0..3b63f2ae24db 100644 >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >> @@ -28,8 +28,6 @@ properties: >>             - enum: >>                 - qcom,msm8996-smmu-v2 >>                 - qcom,msm8998-smmu-v2 >> -              - qcom,sc7180-smmu-v2 >> -              - qcom,sdm845-smmu-v2 > > What about the "Apps SMMU" instances? Those are distinct and don't > have/need the GPU special behaviour, right? Oh, having looked at patch #4, which prompted me go and look at the 845 DTSI in context, now I realise the subtlety I overlooked. So I guess it really was worth resending, ha! Sorry for being thick :) Reviewed-by: Robin Murphy > > Robin. > >>             - const: qcom,smmu-v2 >>         - description: Qcom SoCs implementing "arm,mmu-500" >> @@ -40,6 +38,13 @@ properties: >>                 - qcom,sm8150-smmu-500 >>                 - qcom,sm8250-smmu-500 >>             - const: arm,mmu-500 >> +      - description: Qcom Adreno GPUs implementing "arm,smmu-v2" >> +        items: >> +          - enum: >> +              - qcom,sc7180-smmu-v2 >> +              - qcom,sdm845-smmu-v2 >> +          - const: qcom,adreno-smmu >> +          - const: qcom,smmu-v2 >>         - description: Marvell SoCs implementing "arm,mmu-500" >>           items: >>             - const: marvell,ap806-smmu-500 >>