From: hali@codeaurora.org
To: Archit Taneja <architt@codeaurora.org>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH] drm/msm/mdp5: enable clocks in hw_init and set_irqmask
Date: Wed, 26 Aug 2015 13:55:50 -0000 [thread overview]
Message-ID: <9475e562be69b5c0ec26c4c63e0f83e0.squirrel@www.codeaurora.org> (raw)
In-Reply-To: <1440568263-674-1-git-send-email-architt@codeaurora.org>
Hi Archit,
> mdp5_hw_init and mdp5_set_irqmask configure registers but may not have
> clocks enabled.
>
> Add mdp5_enable/disable calls in these funcs to ensure clocks are
> enabled. We need this until we get proper runtime pm support.
>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
> drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c | 10 ++++++++--
> drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 2 ++
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
> b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
> index b1f73be..9fabfca 100644
> --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
> +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_irq.c
> @@ -24,9 +24,15 @@
> void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
> uint32_t old_irqmask)
> {
> - mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_CLEAR(0),
> + struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
> +
> + mdp5_enable(mdp5_kms);
> +
> + mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0),
> irqmask ^ (irqmask & old_irqmask));
> - mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_EN(0), irqmask);
> + mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), irqmask);
> +
> + mdp5_disable(mdp5_kms);
> }
mdp5_set_irqmask() can be invoked in atomic context, clk_prepare() is not
allowed in this function because it may cause process to sleep. We can
enable the clocks in the caller at initialization.
>
> static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t
> irqstatus)
> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> index 047cb04..2b760f5 100644
> --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c
> @@ -32,6 +32,7 @@ static int mdp5_hw_init(struct msm_kms *kms)
> unsigned long flags;
>
> pm_runtime_get_sync(dev->dev);
> + mdp5_enable(mdp5_kms);
>
> /* Magic unknown register writes:
> *
> @@ -63,6 +64,7 @@ static int mdp5_hw_init(struct msm_kms *kms)
>
> mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
>
> + mdp5_disable(mdp5_kms);
> pm_runtime_put_sync(dev->dev);
>
> return 0;
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> hosted by The Linux Foundation
>
>
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next prev parent reply other threads:[~2015-08-26 13:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-26 5:51 [PATCH] drm/msm/mdp5: enable clocks in hw_init and set_irqmask Archit Taneja
2015-08-26 13:55 ` hali [this message]
2015-08-26 14:18 ` Rob Clark
2015-08-26 15:12 ` hali
2015-08-27 5:06 ` Archit Taneja
2015-08-28 7:56 ` Archit Taneja
2015-08-28 18:18 ` Rob Clark
2015-08-31 5:15 ` Archit Taneja
2015-08-31 11:38 ` Rob Clark
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