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Fri, 28 Feb 2025 11:12:45 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51SBCiIV026781 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Feb 2025 11:12:44 GMT Received: from [10.151.36.43] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 28 Feb 2025 03:12:41 -0800 Message-ID: <94cba308-4c5c-d968-0a4b-e12ce8784bbf@quicinc.com> Date: Fri, 28 Feb 2025 16:42:30 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v1 1/3] arm64: dts: qcom: ipq9574: Add SPI nand support To: Konrad Dybcio , , , , , , , , References: <20250224113742.2829545-1-quic_mdalam@quicinc.com> <20250224113742.2829545-2-quic_mdalam@quicinc.com> <6980c805-92b8-4011-af94-a701a8218548@oss.qualcomm.com> Content-Language: en-US From: Md Sadre Alam In-Reply-To: <6980c805-92b8-4011-af94-a701a8218548@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: kINb6u4Y87Tw7EYKfzVXap-MOHCpq_m4 X-Proofpoint-ORIG-GUID: kINb6u4Y87Tw7EYKfzVXap-MOHCpq_m4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-28_02,2025-02-27_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 phishscore=0 spamscore=0 mlxscore=0 mlxlogscore=832 malwarescore=0 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502280080 On 2/25/2025 2:06 AM, Konrad Dybcio wrote: > On 24.02.2025 12:37 PM, Md Sadre Alam wrote: >> Add SPI NAND support for ipq9574 SoC. >> >> Signed-off-by: Md Sadre Alam >> --- >> * Moved changes in ipq9574-rdp-common.dtsi to separate patch >> >> * Prefixed zero for reg address in qpic_bam and qpic_nand >> >> * For full change history, please refer to https://lore.kernel.org/linux-arm-msm/20241120091507.1404368-8-quic_mdalam@quicinc.com/ >> --- >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 +++++++++++++++++++++++++++ >> 1 file changed, 28 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 942290028972..acbcf507adef 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -447,6 +447,34 @@ tcsr: syscon@1937000 { >> reg = <0x01937000 0x21000>; >> }; >> >> + qpic_bam: dma-controller@7984000 { >> + compatible = "qcom,bam-v1.7.0"; > > v1.7.4 Ok > >> + reg = <0x07984000 0x1c000>; >> + interrupts = ; >> + clocks = <&gcc GCC_QPIC_AHB_CLK>; >> + clock-names = "bam_clk"; >> + #dma-cells = <1>; >> + qcom,ee = <0>; >> + status = "disabled"; >> + }; >> + >> + qpic_nand: spi@79b0000 { >> + compatible = "qcom,ipq9574-snand"; >> + reg = <0x079b0000 0x10000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + clocks = <&gcc GCC_QPIC_CLK>, >> + <&gcc GCC_QPIC_AHB_CLK>, >> + <&gcc GCC_QPIC_IO_MACRO_CLK>; >> + clock-names = "core", "aon", "iom"; >> + dmas = <&qpic_bam 0>, >> + <&qpic_bam 1>, >> + <&qpic_bam 2>; >> + dma-names = "tx", "rx", "cmd"; > > Please make clock-names & dma-names a vertical list, like clocks and dmas > and shift the nodes so that they're sorted by address Ok, will fix and post in next revision. > > Konrad