From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ABF92119; Mon, 25 Nov 2024 07:35:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732520157; cv=none; b=Imgsk1TmFJQ1JEsQrmYBHfQAIDiz2J14zCYR6tc8OoSGuNQt8SiVcGC7gzDkHrETl8q5bc0a8bqTHcErQsuOD2iLPRTRbPYh6SeH5R/NSW0Q03M9YhrLz24I5tI1FFg6xWvqa0h6PJ/0Byt1pyqEn4i2y08MSpyxcnvHIZ6hbhc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732520157; c=relaxed/simple; bh=lIaPAEe/5xyZbTdWkmRj4VZ5612+TEcRS6FQjnJseEU=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=M7V+my0fKGA9RnW3/wyv9tUduDW8OyA4QUz5nEs6D6yh5WlkVMm/bBA/cBWfS/b3Be3hEOCWAsGWAiOLFfO6pwdgLeiXO1fXyn+I2BNI5I2lTSDqFDgtZl15JV8Bur166mP5PKpbt2oJZ6babbBiCFe4hnzIfcYyMjxqmdMpWm8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FYBQeD2l; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FYBQeD2l" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 24433C4CECE; Mon, 25 Nov 2024 07:35:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1732520157; bh=lIaPAEe/5xyZbTdWkmRj4VZ5612+TEcRS6FQjnJseEU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=FYBQeD2lyXCXlnVftx83jDZWSdgyZqUHTVvRuBTTDy3ezqkjuenzhlo7RjQlIUYga rWnPEYdupRjS1RF7gQd3sot/WdPfTGREwux7kvSPTzgqdoqWnLsDBZ/11zNISIg622 2DdI/4lXHpOF75qE1mJipbudWC/4XDO2iklhURZzXa/4UFumF0X1+hDcJ3tGo/rWj5 bxp53OREGZo16QyFvy2D0qPufDY+fxZrAQT/B5oKGYzeue4K/Btk56h2zf+OEvJVOD LRfhcUUqpk/O/150+4T5RcfMh19EQRriO+A6WwUKHoVGYCYqHRzlOFCc6F6I2cR/SU fAaN5E+j/aXsQ== Message-ID: <97a6c471-b146-4625-a3fa-93ee29be4c37@kernel.org> Date: Mon, 25 Nov 2024 08:35:50 +0100 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/2] arm64: dts: qcom: qcs615: add SDHC1 and SDHC2 To: Yuanjie Yang , ulf.hansson@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bhupesh.sharma@linaro.org, andersson@kernel.org, konradybcio@kernel.org Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_tingweiz@quicinc.com, quic_zhgao@quicinc.com References: <20241122065101.1918470-1-quic_yuanjiey@quicinc.com> <20241122065101.1918470-2-quic_yuanjiey@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 25/11/2024 03:20, Yuanjie Yang wrote: > On Fri, Nov 22, 2024 at 01:35:28PM +0100, Krzysztof Kozlowski wrote: >> On 22/11/2024 09:40, Yuanjie Yang wrote: >>> On Fri, Nov 22, 2024 at 08:04:31AM +0100, Krzysztof Kozlowski wrote: >>>> On 22/11/2024 07:51, Yuanjie Yang wrote: >>>>> Add SDHC1 and SDHC2 support to the QCS615 Ride platform. >>>>> >>>>> Signed-off-by: Yuanjie Yang >>>>> --- >>>>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 198 +++++++++++++++++++++++++++ >>>>> 1 file changed, 198 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>>> index 590beb37f441..37c6ab217c96 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi >>>>> @@ -399,6 +399,65 @@ qfprom: efuse@780000 { >>>>> #size-cells = <1>; >>>>> }; >>>>> >>>>> + sdhc_1: mmc@7c4000 { >>>>> + compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; >>>>> + reg = <0x0 0x007c4000 0x0 0x1000>, >>>>> + <0x0 0x007c5000 0x0 0x1000>; >>>>> + reg-names = "hc", >>>>> + "cqhci"; >>>>> + >>>>> + interrupts = , >>>>> + ; >>>>> + interrupt-names = "hc_irq", >>>>> + "pwr_irq"; >>>>> + >>>>> + clocks = <&gcc GCC_SDCC1_AHB_CLK>, >>>>> + <&gcc GCC_SDCC1_APPS_CLK>, >>>>> + <&rpmhcc RPMH_CXO_CLK>, >>>>> + <&gcc GCC_SDCC1_ICE_CORE_CLK>; >>>>> + clock-names = "iface", >>>>> + "core", >>>>> + "xo", >>>>> + "ice"; >>>>> + >>>>> + resets = <&gcc GCC_SDCC1_BCR>; >>>>> + >>>>> + power-domains = <&rpmhpd RPMHPD_CX>; >>>>> + operating-points-v2 = <&sdhc1_opp_table>; >>>>> + iommus = <&apps_smmu 0x02c0 0x0>; >>>>> + interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS >>>>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >>>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >>>>> + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>; >>>>> + interconnect-names = "sdhc-ddr", >>>>> + "cpu-sdhc"; >>>>> + >>>>> + bus-width = <8>; >>>>> + qcom,dll-config = <0x000f642c>; >>>>> + qcom,ddr-config = <0x80040868>; >>>>> + supports-cqe; >>>>> + dma-coherent; >>>>> + mmc-ddr-1_8v; >>>>> + mmc-hs200-1_8v; >>>>> + mmc-hs400-1_8v; >>>>> + mmc-hs400-enhanced-strobe; >>>> >>>> These are properties of memory, not SoC. If the node is disabled, means >>>> memory is not attached to the SoC, right? >>>> >>>>> + status = "disabled"; >>> Thanks, I think qcom,dll-config and qcom,ddr-config are properties of Soc, >>> they are memory configurations that need to be written to the ioaddr. >>> And mmc-ddr-1_8v,mmc-hs200-1_8v,mmc-hs400-1_8v are bus speed config, >>> they indicate the bus speed at which the host contoller can operate. >>> If the node is disabled, which means Soc don't support these properties. >> No, that is not the meaning of node is disabled. When node is disabled, >> it means board does not have attached memory. >> >> Move the memory related properties to the board. > > Thanks, Ok I understand, I will move the memory related > properties(qcom,dll-config and qcom,ddr-config) to the > board dts in next version. What? Why are you talking about these properties? My comment was not under these! Best regards, Krzysztof