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Tue, 20 Jan 2026 12:54:22 -0800 (PST) X-Received: by 2002:a05:6a00:3020:b0:81f:4319:6a0c with SMTP id d2e1a72fcca58-81fa03a1fbfmr13263071b3a.51.1768942461924; Tue, 20 Jan 2026 12:54:21 -0800 (PST) Received: from [192.168.1.7] ([106.222.229.7]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-81fa12b51d9sm12851073b3a.65.2026.01.20.12.54.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 20 Jan 2026 12:54:21 -0800 (PST) Message-ID: <996f47de-5900-4a3a-9372-e5ea3ae31c8b@oss.qualcomm.com> Date: Wed, 21 Jan 2026 02:24:16 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: SM8750: Enable CPUFreq support To: Konrad Dybcio , Jagadeesh Kona Cc: Ajit Pandey , Imran Shaik , Taniya Das , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Sibi Sankar , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio References: <20251211-sm8750-cpufreq-v1-0-394609e8d624@oss.qualcomm.com> <20251211-sm8750-cpufreq-v1-2-394609e8d624@oss.qualcomm.com> <908b64f1-f6ac-4c5e-9c72-1174cba62017@oss.qualcomm.com> <99796cc0-f29b-40d0-b8bb-ebcbcc950b23@oss.qualcomm.com> Content-Language: en-US From: Akhil P Oommen In-Reply-To: <99796cc0-f29b-40d0-b8bb-ebcbcc950b23@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: bxoUQTKN60UeinQo_IaGD7-R4z5K6ZJ2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTIwMDE3NSBTYWx0ZWRfX46acDiRPbWvq VJtZgi+1rKqJtdpWVBiurI6jcpO+sFDc8yrrkfM8hyPRoeHQmqLCHyP6Jktmj2o63AnoS6urGbv NiS2Wll7WClJmBi1JHF0lAffE1vuwjKpyILoCA6UIKAhvTiNQ12bkb9KCYXaCug64UMdCbn3J58 B2nX7ka0LqvoADxSQ8GCS5XLPnJMZqdFXkSFjPDGnd8TYW6WT5Camu10axgZ/AvLEhYm5L7+F8y yw8k5FKRxjx9LO/JdeFFLAptj9olOx1Nts8mycDCJmk3b+FHHGeMAoctAVbIE4owuEN30gOtgel S7T+KlGqLgdXEIlRmF9kwXLuNhB3veCjov/FaOA+dyWHvx1Elu+sqVAD5ym2xPr9m0bqB0ioOw1 nbn8yAYcoPvzSEV4xaAsNLNsaaGnMuOyM39Ze6GV9T6hBh3cuHCZs6AhLABKShmUKWBGJTlxCKE weB682EGKLNZ3HBZEsQ== X-Authority-Analysis: v=2.4 cv=PdfyRyhd c=1 sm=1 tr=0 ts=696feb7f cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=dP73N8aTmtjQGoAWXS14bA==:17 a=IkcTkHD0fZMA:10 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=t2XMIitdhs3okelATYgA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: bxoUQTKN60UeinQo_IaGD7-R4z5K6ZJ2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.20,FMLib:17.12.100.49 definitions=2026-01-20_05,2026-01-20_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 spamscore=0 phishscore=0 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2601150000 definitions=main-2601200175 On 1/20/2026 8:13 PM, Konrad Dybcio wrote: > On 1/20/26 12:25 PM, Akhil P Oommen wrote: >> On 1/20/2026 3:44 PM, Konrad Dybcio wrote: >>> On 1/19/26 8:00 PM, Akhil P Oommen wrote: >>>> On 12/11/2025 12:32 AM, Jagadeesh Kona wrote: >>>>> Add the cpucp mailbox, sram and SCMI nodes required to enable >>>>> the CPUFreq support using the SCMI perf protocol on SM8750 SoCs. >>>>> >>>>> Signed-off-by: Jagadeesh Kona >>>> >>>> Just curious, does this patch enable thermal mitigation for CPU clusters >>>> too? >>> >>> If nothing changed, we have lets-not-explode type mitigations via LMH, >>> but lets-not-burn-the-user would require a skin temp sensor to be >>> wired up, which then could be used to enable some cooling action >> >> In some chipsets, I have noticed that the gpu cooling device throttles >> GPU to the lowest OPP even with not-so-heavy GPU workloads, making it >> unusable-ly slow. My hypothesis was that it was due to unmitigated CPU >> temperature tripping up GPU Tsens. >> >> So, I am wondering if there are any additional CPU cooling related >> changes required to get a reasonable overall performance under thermal >> constraints. > > Yes, something like the aforementioned skin-temp sensor at least.. I suppose this sensor is off-chip and slow to react. > > Today Linux will not throttle the CPUs at all (they're not even declared > as cooling devices) and we sorta agreed that in general it's a good thing > (tm), because otherwise we'd be coding in a cooling profile into the SoC > DTSI without taking into account the cooling capabilities of a given end > device (i.e. in an extreme case, a PC with SM8650 with a cooler that's > 3kg of aluminium vs a Steam Frame headset where the SoC is centimeters > away from your face) > > Currently, we have cooling policies for devices with fans and the only > other action is based on a skin temperature sensor (sc8280xp + x13s). > Everything else is left up to the LMH defaults. AFAIK work is ongoing to > create a more informed solution, that would have to (quite obviously) > live in userland. I can understand that the skin-temp based mitigation is influenced by various design decision outside of the SoC die. But I think there should an on-chip sensor based mitigation which is fast and usually for a short duration which helps to avoid extreme temperature or violating the maximum operating point of the chipset. I guess it should depend only on the SoC characteristics as it is a last resort. It may be implemented in SW (like cooling device for Adreno GPU) or in HW. Probably the LMH hardware you mentioned offers this functionality for CPU clusters. I have no clue. :( I am hoping that if this on-chip mitigation is enabled and wired up correctly for CPU clusters (probably DDR too), it would reduce the unnecessary thermal trips on GPU Tsens and help to reach a performance equilibrium which is reasonably good. -Akhil. > > Konrad