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Fri, 12 Jul 2024 09:54:04 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46C9s3k8011098 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 12 Jul 2024 09:54:03 GMT Received: from [10.216.11.166] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 12 Jul 2024 02:53:58 -0700 Message-ID: <9c3de930-47b7-45a9-bf7e-6e506ea2accc@quicinc.com> Date: Fri, 12 Jul 2024 15:23:55 +0530 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 8/8] arm64: dts: qcom: sm4450: add camera, display and gpu clock controller To: Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Vinod Koul , Vladimir Zapolskiy CC: , , , , Taniya Das , Jagadeesh Kona , Imran Shaik , Satya Priya Kakitapalli References: <20240611133752.2192401-1-quic_ajipan@quicinc.com> <20240611133752.2192401-9-quic_ajipan@quicinc.com> <76f5e3c7-a90b-42d2-8169-e5e2211a14a1@linaro.org> <95a835e2-9fd9-467b-bd0a-8eeb80ddf678@linaro.org> Content-Language: en-US From: Ajit Pandey In-Reply-To: <95a835e2-9fd9-467b-bd0a-8eeb80ddf678@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BQ2C8t1wXptcE0kpNuLPQNXziP4J8OXE X-Proofpoint-ORIG-GUID: BQ2C8t1wXptcE0kpNuLPQNXziP4J8OXE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-12_07,2024-07-11_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 phishscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2407120070 On 7/11/2024 3:25 PM, Konrad Dybcio wrote: > On 3.07.2024 11:16 AM, Ajit Pandey wrote: >> >> >> On 6/13/2024 1:11 PM, Konrad Dybcio wrote: >>> >>> >>> On 6/11/24 15:37, Ajit Pandey wrote: >>>> Add device node for camera, display and graphics clock controller on >>>> Qualcomm SM4450 platform. >>>> >>>> Signed-off-by: Ajit Pandey >>>> --- >>> >>> None of these nodes reference a power domain (which would usually be >>> CX/MX/MMCX). This way, the RPMhPDs will never be scaled. >>> >>> The current upstream implementation only allows one power domain to be >>> scaled, but that's better than none (see other DTs for recent SoCs). >>> >>> Konrad >> >> SM4450 doesn't support MMCX and CX/MX domains will remain active so >> power-domains property is actually not required for SM4450 clock nodes. > > It's not only about them being active.. some PLLs require e.g. MX to be > at a certain level, or the system will be unstable > > Konrad With active I mean CX/MX rails will be default running at minimum level required for clock controllers. Adding power-domains property for CX/MX rails is like a redundant code as that will also scale such rails at default specified minimum level only. Also we hadn't added such property for other targets DT nodes to scale up CX/MX at minimum level. -- Thanks, and Regards Ajit