Re: [PATCH v2 1/8] dt-bindings: PCI: Add binding for qps615

[Krishna Chaitanya Chundru <quic_krichai@quicinc.com>]

On 8/3/2024 4:30 PM, Dmitry Baryshkov wrote:
> On Sat, Aug 03, 2024 at 08:52:47AM GMT, Krishna chaitanya chundru wrote:
>> Add binding describing the Qualcomm PCIe switch, QPS615,
>> which provides Ethernet MAC integrated to the 3rd downstream port
>> and two downstream PCIe ports.
>>
>> Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> ---
>>   .../devicetree/bindings/pci/qcom,qps615.yaml       | 191 +++++++++++++++++++++
>>   1 file changed, 191 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,qps615.yaml b/Documentation/devicetree/bindings/pci/qcom,qps615.yaml
>> new file mode 100644
>> index 000000000000..ea0c953ee56f
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/qcom,qps615.yaml
>> @@ -0,0 +1,191 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/qcom,qps615.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm QPS615 PCIe switch
>> +
>> +maintainers:
>> +  - Krishna chaitanya chundru <quic_krichai@quicinc.com>
>> +
>> +description: |
>> +  Qualcomm QPS615 PCIe switch has one upstream and three downstream
>> +  ports. The 3rd downstream port has integrated endpoint device of
>> +  Ethernet MAC. Other two downstream ports are supposed to connect
>> +  to external device.
>> +
>> +  The QPS615 PCIe switch can be configured through I2C interface before
>> +  PCIe link is established to change FTS, ASPM related entry delays,
>> +  tx amplitude etc for better power efficiency and functionality.
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - pci1179,0623
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  qcom,qps615-controller:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description:
>> +      Reference to the I2C client used to do configure qps615
>> +
>> +  vdd18-supply: true
>> +
>> +  vdd09-supply: true
>> +
>> +  vddc-supply: true
>> +
>> +  vddio1-supply: true
>> +
>> +  vddio2-supply: true
>> +
>> +  vddio18-supply: true
>> +
>> +  reset-gpios:
>> +    maxItems: 1
>> +    description:
>> +      GPIO controlling the RESX# pin.
>> +
>> +  qps615,axi-clk-freq-hz:
>> +    description:
>> +      AXI clock which internal bus of the switch.
> 
> Is it a clock or clock rate?
It is clock ony.
> 
>> +
>> +  qcom,l0s-entry-delay-ns:
>> +    description: Aspm l0s entry delay in nanoseconds.
> 
> I'd say, from the property name it is obvious that it comes in
> nanoseconds.
> 
I will remove the description from these properties.
>> +
>> +  qcom,l1-entry-delay-ns:
>> +    description: Aspm l1 entry delay in nanoseconds.
>> +
>> +  qcom,tx-amplitude-millivolt:
>> +    $ref: /schemas/types.yaml#/definitions/uint32
>> +    description: Change Tx Margin setting for low power consumption.
>> +
>> +  qcom,no-dfe:
>> +    type: boolean
>> +    description: Disables DFE (Decision Feedback Equalizer).
>> +
>> +  qcom,nfts:
>> +    $ref: /schemas/types.yaml#/definitions/uint8
>> +    description:
>> +      Fast Training Sequence (FTS) is the mechanism that
>> +      is used for bit and Symbol lock.
> 
> Doesn't help to understand what it is and what the value means.
> 
I will update the description, this property represents number
of fast training sequence needs to be used for link transition
from L0s to L0.

- Krishna Chaitanya.
>>  >> +allOf:
>> +  - $ref: /schemas/pci/pci-bus-common.yaml#
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: pci1179,0623
>> +      required:
>> +        - compatible
>> +    then:
>> +      required:
>> +        - vdd18-supply
>> +        - vdd09-supply
>> +        - vddc-supply
>> +        - vddio1-supply
>> +        - vddio2-supply
>> +        - vddio18-supply
>> +        - qcom,qps615-controller
>> +        - reset-gpios
>> +
>> +patternProperties:
>> +  "@1?[0-9a-f](,[0-7])?$":
>> +    type: object
>> +    $ref: qcom,qps615.yaml#
>> +    additionalProperties: true
>> +
>> +additionalProperties: true
>> +
>> +examples:
>> +  - |
>> +
>> +    #include <dt-bindings/gpio/gpio.h>
>> +
>> +    pcie {
>> +        #address-cells = <3>;
>> +        #size-cells = <2>;
>> +
>> +        pcie@0 {
>> +            device_type = "pci";
>> +            reg = <0x0 0x0 0x0 0x0 0x0>;
>> +
>> +            #address-cells = <3>;
>> +            #size-cells = <2>;
>> +            ranges;
>> +
>> +            pcie@0,0 {
>> +                compatible = "pci1179,0623";
>> +                reg = <0x10000 0x0 0x0 0x0 0x0>;
>> +                device_type = "pci";
>> +                #address-cells = <3>;
>> +                #size-cells = <2>;
>> +                ranges;
>> +
>> +                qcom,qps615-controller = <&qps615_controller>;
> 
> Where is the corresponding device?
> 
>> +
>> +                vdd18-supply = <&vdd>;
>> +                vdd09-supply = <&vdd>;
>> +                vddc-supply = <&vdd>;
>> +                vddio1-supply = <&vdd>;
>> +                vddio2-supply = <&vdd>;
>> +                vddio18-supply = <&vdd>;
>> +
>> +                reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
>> +
>> +                pcie@1,0 {
>> +                    reg = <0x20800 0x0 0x0 0x0 0x0>;
>> +                    #address-cells = <3>;
>> +                    #size-cells = <2>;
>> +                    device_type = "pci";
>> +                    ranges;
>> +
>> +                    qcom,no-dfe;
>> +                };
>> +
>> +                pcie@2,0 {
>> +                    reg = <0x21000 0x0 0x0 0x0 0x0>;
>> +                    #address-cells = <3>;
>> +                    #size-cells = <2>;
>> +                    device_type = "pci";
>> +                    ranges;
>> +
>> +                    qcom,nfts = /bits/ 8 <10>;
>> +                };
>> +
>> +                pcie@3,0 {
>> +                    reg = <0x21800 0x0 0x0 0x0 0x0>;
>> +                    #address-cells = <3>;
>> +                    #size-cells = <2>;
>> +                    device_type = "pci";
>> +                    ranges;
>> +
>> +                    qcom,tx-amplitude-millivolt = <10>;
>> +
>> +                         pcie@0,0 {
> 
> Wrong indentation.
> 
>> +                              reg = <0x40000 0x0 0x0 0x0 0x0>;
>> +                              #address-cells = <3>;
>> +                              #size-cells = <2>;
>> +                              device_type = "pci";
>> +                              ranges;
>> +
>> +                              qcom,l1-entry-delay-ns = <10>;
>> +                         };
>> +
>> +                         pcie@0,1 {
>> +                              reg = <0x40100 0x0 0x0 0x0 0x0>;
>> +                              #address-cells = <3>;
>> +                              #size-cells = <2>;
>> +                              device_type = "pci";
>> +                              ranges;
>> +
>> +                              qcom,l0s-entry-delay-ns = <10>;
>> +                         };
>> +                };
>> +            };
>> +        };
>> +    };
>>
>> -- 
>> 2.34.1
>>
>