From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97E94C6FA86 for ; Mon, 26 Sep 2022 10:39:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235956AbiIZKjz (ORCPT ); Mon, 26 Sep 2022 06:39:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236243AbiIZKio (ORCPT ); Mon, 26 Sep 2022 06:38:44 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F399652454 for ; Mon, 26 Sep 2022 03:22:36 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id k10so10084893lfm.4 for ; Mon, 26 Sep 2022 03:22:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date; bh=zkcOb24Evi1ksE1lwkoQgL5n/a7zuiGn5FgVHGwVjjk=; b=ccclXjfhbZ9g6sNaMs7j8J17AqDo8SuTkaQsosFYpKCZAot5wuamdGIH9ecTb7TAPz z9hu4DV98CZo7qo/B2ZKQRWZS7s5fjrzdMq49PJy91ayuZBF/IXyGwcmsLqPtdCSw46X GlC3Sqm/Sjdi/t3Jgx5wyrWsSQJSkMaPBq+f2L65OyAkr+mHBcaz6hK4Iga0hRAdQKJQ YkqMOogeSQai2WNgcUZmh13NVUpyIh0tQhFFjpYQoOmfv6b0PZ+Cn/1d+G/yvHp0rzww Wep8gfekmgcywOKFOrJtzMBJTsQvZ2q8Y2IuIkn8w+vQ04087NbbnkjybP74gBrGEGmE EeKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date; bh=zkcOb24Evi1ksE1lwkoQgL5n/a7zuiGn5FgVHGwVjjk=; b=L48S3rb0xGl97m90hiBM6IBMq30F5X40Q0gPjvp9BticuRKoRZIw+fonhKUgVKajHC yMtuWU5YUE4Rks211gjCWr0F75NQct2E4DBvZKfbWHkEYPcmSZzJqDH7FZs+bXPE4jeN jyMEfAGY2poCso+mqqhpO8wRMQL7RSUW+H/a9mwgKhJstt3r2JAdqsusYZUSdvXxhZsa DpcYTFxEo78iSWEnl9GcmqU5F3BKr/WNaE9TUme0Tlu3XXP7paVobT6IpyRPVqZ/Ig3O rMmXtzETpWf0HV3zrV+QR2uy051A/+FyTvrCbWlX3iWfuqCE0IRuikbp0BglKQMKMwE4 GD1w== X-Gm-Message-State: ACrzQf2FY1o65JNWS8Zsc05jgUOw5lPZH3mI2WCqH0JLbglzyiO02UOz E46nO9Qf8zdOtwcIedwh7N6PkQ== X-Google-Smtp-Source: AMsMyM7LGod3qiCYNpJ7TH3RuskDdwJcAyDevsVmmvUUQSsLPsbj1fJLvCd60O4HF8gDG91s1bw3+Q== X-Received: by 2002:a05:6512:685:b0:49f:4929:4c6e with SMTP id t5-20020a056512068500b0049f49294c6emr9222096lfe.642.1664187740702; Mon, 26 Sep 2022 03:22:20 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x28-20020a056512047c00b00497a32e2576sm2487979lfd.32.2022.09.26.03.22.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Sep 2022 03:22:20 -0700 (PDT) Message-ID: <9f66ac8e-6d35-3046-e237-936bc10ba86f@linaro.org> Date: Mon, 26 Sep 2022 13:22:19 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v4 1/6] phy: qcom-qmp-pcie: split register tables into common and extra parts Content-Language: en-GB To: Johan Hovold Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org References: <20220924160302.285875-1-dmitry.baryshkov@linaro.org> <20220924160302.285875-2-dmitry.baryshkov@linaro.org> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 26/09/2022 09:32, Johan Hovold wrote: > On Sat, Sep 24, 2022 at 07:02:57PM +0300, Dmitry Baryshkov wrote: >> SM8250 configuration tables are split into two parts: the common one and >> the PHY-specific tables. Make this split more formal. Rather than having >> a blind renamed copy of all QMP table fields, add separate struct >> qmp_phy_cfg_tables and add two instances of this structure to the struct >> qmp_phy_cfg. Later on this will be used to support different PHY modes >> (RC vs EP). >> >> Signed-off-by: Dmitry Baryshkov >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 129 ++++++++++++++--------- >> 1 file changed, 77 insertions(+), 52 deletions(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> index 7aff3f9940a5..30806816c8b0 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> @@ -1300,31 +1300,30 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { >> QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), >> }; >> >> -/* struct qmp_phy_cfg - per-PHY initialization config */ >> -struct qmp_phy_cfg { >> - int lanes; >> - >> - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ >> +struct qmp_phy_cfg_tables { >> const struct qmp_phy_init_tbl *serdes_tbl; >> int serdes_tbl_num; >> - const struct qmp_phy_init_tbl *serdes_tbl_sec; >> - int serdes_tbl_num_sec; >> const struct qmp_phy_init_tbl *tx_tbl; >> int tx_tbl_num; >> - const struct qmp_phy_init_tbl *tx_tbl_sec; >> - int tx_tbl_num_sec; >> const struct qmp_phy_init_tbl *rx_tbl; >> int rx_tbl_num; >> - const struct qmp_phy_init_tbl *rx_tbl_sec; >> - int rx_tbl_num_sec; >> const struct qmp_phy_init_tbl *pcs_tbl; >> int pcs_tbl_num; >> - const struct qmp_phy_init_tbl *pcs_tbl_sec; >> - int pcs_tbl_num_sec; >> const struct qmp_phy_init_tbl *pcs_misc_tbl; >> int pcs_misc_tbl_num; >> - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; >> - int pcs_misc_tbl_num_sec; >> +}; >> + >> +/* struct qmp_phy_cfg - per-PHY initialization config */ >> +struct qmp_phy_cfg { >> + int lanes; >> + >> + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ >> + struct qmp_phy_cfg_tables common; >> + /* >> + * Additional init sequence for PHY blocks, providing additional >> + * register programming. Unless required it can be left omitted. >> + */ >> + struct qmp_phy_cfg_tables *extra; >> >> /* clock ids to be requested */ >> const char * const *clk_list; > >> @@ -1949,31 +1974,31 @@ static int qmp_pcie_power_on(struct phy *phy) >> } >> >> /* Tx, Rx, and PCS configurations */ >> - qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); >> - qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1); >> + qmp_pcie_configure_lane(tx, cfg->regs, cfg->common.tx_tbl, cfg->common.tx_tbl_num, 1); >> + qmp_pcie_configure_lane(tx, cfg->regs, cfg->extra->tx_tbl, cfg->extra->tx_tbl_num, 1); > > Hmm. How did you test this? > > With your later versions of this series, cfg->extra is generally NULL so > this would dereference a NULL pointer. I must admit, I tested this only on sm8450. Mea culpa. > > Johan -- With best wishes Dmitry