From mboxrd@z Thu Jan  1 00:00:00 1970
From: Wan ZongShun <mcuos.com@gmail.com>
Subject: Re: [PATCH V2] drivers: rtc: Add support for Qualcomm PMIC8xxx RTC
Date: Tue, 10 May 2011 09:44:09 +0800
Message-ID: <BANLkTimPeLmQiJqejk2ZNCJgQLc9GB=WRQ@mail.gmail.com>
References: <1304574535-23710-1-git-send-email-aghayal@codeaurora.org> <4DC7D2E8.10105@codeaurora.org>
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To: Anirudh Ghayal <aghayal@codeaurora.org>
Cc: rtc-linux@googlegroups.com, Andrew Morton <akpm@linux-foundation.org>, Lars-Peter Clausen <lars@metafoo.de>, Alessandro Zummo <a.zummo@towertech.it>, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org

2011/5/9 Anirudh Ghayal <aghayal@codeaurora.org>:
> Hi Peter, Wan,
>
> I have updated the patch with your suggested changes.
> Could you please re-review this patch.

Acked-by: Wan ZongShun <mcuos.com@gmail.com>

thanks!

>
> Thank you,
> ~Anirudh
>
> On 5/5/2011 11:18 AM, Anirudh Ghayal wrote:
>>
>> This patch adds support for PMIC8xxx based RTC.
>> PMIC8xxx is Qualcomm's power management IC that
>> internally houses an RTC module. This driver
>> communicates with the PMIC module over SSBI bus.
>>
>> Cc: Wan ZongShun<mcuos.com@gmail.com>
>> Cc: Andrew Morton<akpm@linux-foundation.org>
>> Cc: Lars-Peter Clausen<lars@metafoo.de>
>> Signed-off-by: Anirudh Ghayal<aghayal@codeaurora.org>
>> ---
>> =C2=A0drivers/rtc/Kconfig =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=
 =C2=A0 10 +
>> =C2=A0drivers/rtc/Makefile =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0=
 =C2=A01 +
>> =C2=A0drivers/rtc/rtc-pm8xxx.c =C2=A0 =C2=A0 =C2=A0 | =C2=A0568
>> ++++++++++++++++++++++++++++++++++++++++
>> =C2=A0include/linux/mfd/pm8xxx/rtc.h | =C2=A0 25 ++
>> =C2=A04 files changed, 604 insertions(+), 0 deletions(-)
>> =C2=A0create mode 100644 drivers/rtc/rtc-pm8xxx.c
>> =C2=A0create mode 100644 include/linux/mfd/pm8xxx/rtc.h
>>
>> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
>> index e187887..39b7032 100644
>> --- a/drivers/rtc/Kconfig
>> +++ b/drivers/rtc/Kconfig
>> @@ -985,6 +985,16 @@ config RTC_DRV_LPC32XX
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0This driver can also be buillt as =
a module. If so, the module
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0will be called rtc-lpc32xx.
>>
>> +config RTC_DRV_PM8XXX
>> + =C2=A0 =C2=A0 =C2=A0 tristate "Qualcomm PMIC8XXX RTC"
>> + =C2=A0 =C2=A0 =C2=A0 depends on MFD_PM8XXX
>> + =C2=A0 =C2=A0 =C2=A0 help
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 If you say yes here you get support fo=
r the
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 Qualcomm PMIC8XXX RTC.
>> +
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 To compile this driver as a module, ch=
oose M here: the
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 module will be called rtc-pm8xxx.
>> +
>> =C2=A0config RTC_DRV_TEGRA
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0tristate "NVIDIA Tegra Internal RTC drive=
r"
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0depends on RTC_CLASS&& =C2=A0ARCH_TEGRA
>> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
>> index ca91c3c..40a6e66 100644
>> --- a/drivers/rtc/Makefile
>> +++ b/drivers/rtc/Makefile
>> @@ -74,6 +74,7 @@ obj-$(CONFIG_RTC_DRV_PCF2123) +=3D rtc-pcf2123.o
>> =C2=A0obj-$(CONFIG_RTC_DRV_PCF50633) =C2=A0 =C2=A0 =C2=A0 =C2=A0+=3D=
 rtc-pcf50633.o
>> =C2=A0obj-$(CONFIG_RTC_DRV_PL030) =C2=A0 +=3D rtc-pl030.o
>> =C2=A0obj-$(CONFIG_RTC_DRV_PL031) =C2=A0 +=3D rtc-pl031.o
>> +obj-$(CONFIG_RTC_DRV_PM8XXX) =C2=A0 =C2=A0+=3D rtc-pm8xxx.o
>> =C2=A0obj-$(CONFIG_RTC_DRV_PS3) =C2=A0 =C2=A0 +=3D rtc-ps3.o
>> =C2=A0obj-$(CONFIG_RTC_DRV_PXA) =C2=A0 =C2=A0 +=3D rtc-pxa.o
>> =C2=A0obj-$(CONFIG_RTC_DRV_R9701) =C2=A0 +=3D rtc-r9701.o
>> diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c
>> new file mode 100644
>> index 0000000..95e3911
>> --- /dev/null
>> +++ b/drivers/rtc/rtc-pm8xxx.c
>> @@ -0,0 +1,568 @@
>> +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or mo=
dify
>> + * it under the terms of the GNU General Public License version 2 a=
nd
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =C2=A0See t=
he
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include<linux/module.h>
>> +#include<linux/init.h>
>> +#include<linux/rtc.h>
>> +#include<linux/pm.h>
>> +#include<linux/slab.h>
>> +#include<linux/spinlock.h>
>> +
>> +#include<linux/mfd/pm8xxx/core.h>
>> +#include<linux/mfd/pm8xxx/rtc.h>
>> +
>> +
>> +/* RTC Register offsets from RTC CTRL REG */
>> +#define PM8XXX_ALARM_CTRL_OFFSET 0x01
>> +#define PM8XXX_RTC_WRITE_OFFSET 0x02
>> +#define PM8XXX_RTC_READ_OFFSET 0x06
>> +#define PM8XXX_ALARM_RW_OFFSET 0x0A
>> +
>> +/* RTC_CTRL register bit fields */
>> +#define PM8xxx_RTC_ENABLE =C2=A0 =C2=A0 =C2=A0BIT(7)
>> +#define PM8xxx_RTC_ALARM_ENABLE =C2=A0 =C2=A0 =C2=A0 =C2=A0BIT(1)
>> +#define PM8xxx_RTC_ALARM_CLEAR =C2=A0BIT(0)
>> +
>> +#define NUM_8_BIT_RTC_REGS =C2=A0 =C2=A0 0x4
>> +
>> +/**
>> + * struct pm8xxx_rtc - rtc driver internal structure
>> + * @rtc: rtc device for this driver
>> + * @rtc_alarm_irq: rtc alarm irq number
>> + */
>> +struct pm8xxx_rtc {
>> + =C2=A0 =C2=A0 =C2=A0 struct rtc_device *rtc;
>> + =C2=A0 =C2=A0 =C2=A0 int rtc_alarm_irq;
>> + =C2=A0 =C2=A0 =C2=A0 int rtc_base;
>> + =C2=A0 =C2=A0 =C2=A0 int rtc_read_base;
>> + =C2=A0 =C2=A0 =C2=A0 int rtc_write_base;
>> + =C2=A0 =C2=A0 =C2=A0 int alarm_rw_base;
>> + =C2=A0 =C2=A0 =C2=A0 u8 =C2=A0ctrl_reg;
>> + =C2=A0 =C2=A0 =C2=A0 struct device *rtc_dev;
>> + =C2=A0 =C2=A0 =C2=A0 spinlock_t ctrl_reg_lock;
>> +};
>> +
>> +/*
>> + * The RTC registers need to be read/written one byte at a time. Th=
is is
>> a
>> + * hardware limitation.
>> + */
>> +
>> +static int pm8xxx_read_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_v=
al,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 int base, int count)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 int i, rc;
>> + =C2=A0 =C2=A0 =C2=A0 struct device *parent =3D rtc_dd->rtc_dev->pa=
rent;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i< =C2=A0count; i++) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_rea=
db(parent, base + i,&rtc_val[i]);
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) =
{
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 dev_err(rtc_dd->rtc_dev, "PM8xxx read failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 return rc;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 return 0;
>> +}
>> +
>> +static int pm8xxx_write_wrapper(struct pm8xxx_rtc *rtc_dd, u8 *rtc_=
val,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 int base, int count)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 int i, rc;
>> + =C2=A0 =C2=A0 =C2=A0 struct device *parent =3D rtc_dd->rtc_dev->pa=
rent;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i< =C2=A0count; i++) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_wri=
teb(parent, base + i, rtc_val[i]);
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) =
{
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 dev_err(rtc_dd->rtc_dev, "PM8xxx write failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 return rc;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 return 0;
>> +}
>> +
>> +
>> +/*
>> + * Steps to write the RTC registers.
>> + * 1. Disable alarm if enabled.
>> + * 2. Write 0x00 to LSB.
>> + * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0].
>> + * 4. Enable alarm if disabled in step 1.
>> + */
>> +static int
>> +pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 int rc;
>> + =C2=A0 =C2=A0 =C2=A0 unsigned long secs, irq_flags;
>> + =C2=A0 =C2=A0 =C2=A0 u8 value[4], reg =3D 0, alarm_enabled =3D 0, =
ctrl_reg;
>> + =C2=A0 =C2=A0 =C2=A0 struct pm8xxx_rtc *rtc_dd =3D dev_get_drvdata=
(dev);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_tm_to_time(tm,&secs);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 value[0] =3D secs& =C2=A00xFF;
>> + =C2=A0 =C2=A0 =C2=A0 value[1] =3D (secs>> =C2=A08)& =C2=A00xFF;
>> + =C2=A0 =C2=A0 =C2=A0 value[2] =3D (secs>> =C2=A016)& =C2=A00xFF;
>> + =C2=A0 =C2=A0 =C2=A0 value[3] =3D (secs>> =C2=A024)& =C2=A00xFF;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 dev_dbg(dev, "Seconds value to be written to =
RTC =3D %lu\n", secs);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq=
_flags);
>> + =C2=A0 =C2=A0 =C2=A0 ctrl_reg =3D rtc_dd->ctrl_reg;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 if (ctrl_reg& =C2=A0PM8xxx_RTC_ALARM_ENABLE) =
{
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 alarm_enabled =3D=
 1;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ctrl_reg&=3D ~PM8=
xxx_RTC_ALARM_ENABLE;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_wri=
te_wrapper(rtc_dd,&ctrl_reg,
>> rtc_dd->rtc_base,
>> +
>> 1);
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) =
{
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 dev_err(dev, "PM8xxx write failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 goto rtc_rw_fail;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>> + =C2=A0 =C2=A0 =C2=A0 } else
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 spin_unlock_irqre=
store(&rtc_dd->ctrl_reg_lock, irq_flags);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /* Write Byte[1], Byte[2], Byte[3], Byte[0] *=
/
>> + =C2=A0 =C2=A0 =C2=A0 /* Write 0 to Byte[0] */
>> + =C2=A0 =C2=A0 =C2=A0 reg =3D 0;
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_write_wrapper(rtc_dd,&reg, rtc_=
dd->rtc_write_base, 1);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "PM8=
xxx write failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto rtc_rw_fail;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /* Write Byte[1], Byte[2], Byte[3] */
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_write_wrapper(rtc_dd, value + 1=
,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rtc_=
dd->rtc_write_base + 1, 3);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "Wri=
te to RTC registers failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto rtc_rw_fail;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /* Write Byte[0] */
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_write_wrapper(rtc_dd, value, rt=
c_dd->rtc_write_base,
>> 1);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "Wri=
te to RTC register failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto rtc_rw_fail;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 if (alarm_enabled) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ctrl_reg |=3D PM8=
xxx_RTC_ALARM_ENABLE;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_wri=
te_wrapper(rtc_dd,&ctrl_reg,
>> rtc_dd->rtc_base,
>> +
>> 1);
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) =
{
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 dev_err(dev, "PM8xxx write failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 goto rtc_rw_fail;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->ctrl_reg =3D ctrl_reg;
>> +
>> +rtc_rw_fail:
>> + =C2=A0 =C2=A0 =C2=A0 if (alarm_enabled)
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 spin_unlock_irqre=
store(&rtc_dd->ctrl_reg_lock, irq_flags);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 return rc;
>> +}
>> +
>> +static int
>> +pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 int rc;
>> + =C2=A0 =C2=A0 =C2=A0 u8 value[4], reg;
>> + =C2=A0 =C2=A0 =C2=A0 unsigned long secs;
>> + =C2=A0 =C2=A0 =C2=A0 struct pm8xxx_rtc *rtc_dd =3D dev_get_drvdata=
(dev);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_read_wrapper(rtc_dd, value, rtc=
_dd->rtc_read_base,
>> +
>> NUM_8_BIT_RTC_REGS);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "RTC=
 time read failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return rc;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /*
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0* Read the LSB again and check if there=
 has been a carry over.
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0* If there is, redo the read operation.
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_read_wrapper(rtc_dd,&reg, rtc_d=
d->rtc_read_base, 1);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "PM8=
xxx read failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return rc;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 if (unlikely(reg< =C2=A0value[0])) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_rea=
d_wrapper(rtc_dd, value,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rtc_dd->rtc_read_base,
>> NUM_8_BIT_RTC_REGS);
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) =
{
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 dev_err(dev, "RTC time read failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 return rc;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 secs =3D value[0] | (value[1]<< =C2=A08) | (v=
alue[2]<< =C2=A016) \
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
 =C2=A0 =C2=A0 =C2=A0 | (value[3]<< =C2=A024);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_time_to_tm(secs, tm);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D rtc_valid_tm(tm);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "Inv=
alid time read from PM8xxx\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return rc;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 dev_dbg(dev, "secs =3D %lu, h:m:s =3D=3D %d:%=
d:%d, d/m/y =3D %d/%d/%d\n",
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 tm->tm_mday, tm->tm_mon, tm->tm_year);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 return 0;
>> +}
>> +
>> +static int
>> +pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 int rc;
>> + =C2=A0 =C2=A0 =C2=A0 u8 value[4], ctrl_reg;
>> + =C2=A0 =C2=A0 =C2=A0 unsigned long secs, secs_rtc, irq_flags;
>> + =C2=A0 =C2=A0 =C2=A0 struct pm8xxx_rtc *rtc_dd =3D dev_get_drvdata=
(dev);
>> + =C2=A0 =C2=A0 =C2=A0 struct rtc_time rtc_tm;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_tm_to_time(&alarm->time,&secs);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /*
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0* Read the current RTC time and verify =
if the alarm time is in
>> the
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0* past. If yes, return invalid.
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0*/
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_rtc_read_time(dev,&rtc_tm);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "Una=
mble to read RTC time\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -EINVAL;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_tm_to_time(&rtc_tm,&secs_rtc);
>> + =C2=A0 =C2=A0 =C2=A0 if (secs< =C2=A0secs_rtc) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "Try=
ing to set alarm in the past\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -EINVAL;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 value[0] =3D secs& =C2=A00xFF;
>> + =C2=A0 =C2=A0 =C2=A0 value[1] =3D (secs>> =C2=A08)& =C2=A00xFF;
>> + =C2=A0 =C2=A0 =C2=A0 value[2] =3D (secs>> =C2=A016)& =C2=A00xFF;
>> + =C2=A0 =C2=A0 =C2=A0 value[3] =3D (secs>> =C2=A024)& =C2=A00xFF;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq=
_flags);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_write_wrapper(rtc_dd, value, rt=
c_dd->alarm_rw_base,
>> +
>> NUM_8_BIT_RTC_REGS);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "Wri=
te to RTC ALARM registers failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto rtc_rw_fail;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 ctrl_reg =3D rtc_dd->ctrl_reg;
>> + =C2=A0 =C2=A0 =C2=A0 ctrl_reg =3D (alarm->enabled) ? (ctrl_reg | P=
M8xxx_RTC_ALARM_ENABLE)
>> :
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (ctr=
l_reg&
>> =C2=A0~PM8xxx_RTC_ALARM_ENABLE);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_write_wrapper(rtc_dd,&ctrl_reg,=
 rtc_dd->rtc_base, 1);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "PM8=
xxx write failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto rtc_rw_fail;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->ctrl_reg =3D ctrl_reg;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 dev_dbg(dev, "Alarm Set for h:r:s=3D%d:%d:%d,=
 d/m/y=3D%d/%d/%d\n",
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 alarm->time.tm_hour, alarm->time.tm_min,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 alarm->time.tm_sec, alarm->time.tm_mday,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 alarm->time.tm_mon, alarm->time.tm_year);
>> +rtc_rw_fail:
>> + =C2=A0 =C2=A0 =C2=A0 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock=
, irq_flags);
>> + =C2=A0 =C2=A0 =C2=A0 return rc;
>> +}
>> +
>> +static int
>> +pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 int rc;
>> + =C2=A0 =C2=A0 =C2=A0 u8 value[4];
>> + =C2=A0 =C2=A0 =C2=A0 unsigned long secs;
>> + =C2=A0 =C2=A0 =C2=A0 struct pm8xxx_rtc *rtc_dd =3D dev_get_drvdata=
(dev);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_read_wrapper(rtc_dd, value, rtc=
_dd->alarm_rw_base,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 NUM_8_BIT_RTC_REGS);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "RTC=
 alarm time read failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return rc;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 secs =3D value[0] | (value[1]<< =C2=A08) | (v=
alue[2]<< =C2=A016) | \
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
 =C2=A0 =C2=A0 =C2=A0 =C2=A0(value[3]<< =C2=A024);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_time_to_tm(secs,&alarm->time);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D rtc_valid_tm(&alarm->time);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "Inv=
alid time read from PM8xxx\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return rc;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 dev_dbg(dev, "Alarm set for - h:r:s=3D%d:%d:%=
d, d/m/y=3D%d/%d/%d\n",
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 alarm->time.tm_ho=
ur, alarm->time.tm_min,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 alarm->time.tm_sec, alarm->time.=
tm_mday,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 alarm->time.tm_mon, alarm->time.=
tm_year);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 return 0;
>> +}
>> +
>> +
>> +static int
>> +pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable=
)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 int rc;
>> + =C2=A0 =C2=A0 =C2=A0 unsigned long irq_flags;
>> + =C2=A0 =C2=A0 =C2=A0 struct pm8xxx_rtc *rtc_dd =3D dev_get_drvdata=
(dev);
>> + =C2=A0 =C2=A0 =C2=A0 u8 ctrl_reg;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq=
_flags);
>> + =C2=A0 =C2=A0 =C2=A0 ctrl_reg =3D rtc_dd->ctrl_reg;
>> + =C2=A0 =C2=A0 =C2=A0 ctrl_reg =3D (enable) ? (ctrl_reg | PM8xxx_RT=
C_ALARM_ENABLE) :
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 (ctrl_reg& =C2=A0~PM8xxx_RTC_ALA=
RM_ENABLE);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_write_wrapper(rtc_dd,&ctrl_reg,=
 rtc_dd->rtc_base, 1);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev, "PM8=
xxx write failed\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto rtc_rw_fail;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->ctrl_reg =3D ctrl_reg;
>> +
>> +rtc_rw_fail:
>> + =C2=A0 =C2=A0 =C2=A0 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock=
, irq_flags);
>> + =C2=A0 =C2=A0 =C2=A0 return rc;
>> +}
>> +
>> +static struct rtc_class_ops pm8xxx_rtc_ops =3D {
>> + =C2=A0 =C2=A0 =C2=A0 .read_time =C2=A0 =C2=A0 =C2=A0=3D pm8xxx_rtc=
_read_time,
>> + =C2=A0 =C2=A0 =C2=A0 .set_alarm =C2=A0 =C2=A0 =C2=A0=3D pm8xxx_rtc=
_set_alarm,
>> + =C2=A0 =C2=A0 =C2=A0 .read_alarm =C2=A0 =C2=A0 =3D pm8xxx_rtc_read=
_alarm,
>> + =C2=A0 =C2=A0 =C2=A0 .alarm_irq_enable =3D pm8xxx_rtc_alarm_irq_en=
able,
>> +};
>> +
>> +static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 struct pm8xxx_rtc *rtc_dd =3D dev_id;
>> + =C2=A0 =C2=A0 =C2=A0 u8 ctrl_reg;
>> + =C2=A0 =C2=A0 =C2=A0 int rc;
>> + =C2=A0 =C2=A0 =C2=A0 unsigned long irq_flags;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC=
_AF);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq=
_flags);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /* Clear the alarm enable bit */
>> + =C2=A0 =C2=A0 =C2=A0 ctrl_reg =3D rtc_dd->ctrl_reg;
>> + =C2=A0 =C2=A0 =C2=A0 ctrl_reg&=3D ~PM8xxx_RTC_ALARM_ENABLE;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_write_wrapper(rtc_dd,&ctrl_reg,=
 rtc_dd->rtc_base, 1);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 spin_unlock_irqre=
store(&rtc_dd->ctrl_reg_lock, irq_flags);
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(rtc_dd->r=
tc_dev, "PM8xxx write failed!\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto rtc_alarm_ha=
ndled;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->ctrl_reg =3D ctrl_reg;
>> + =C2=A0 =C2=A0 =C2=A0 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock=
, irq_flags);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /* Clear RTC alarm register */
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_read_wrapper(rtc_dd,&ctrl_reg, =
rtc_dd->rtc_base +
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
 =C2=A0 =C2=A0 =C2=A0 PM8XXX_ALARM_CTRL_OFFSET,
>> 1);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(rtc_dd->r=
tc_dev, "PM8xxx write failed!\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto rtc_alarm_ha=
ndled;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 ctrl_reg&=3D ~PM8xxx_RTC_ALARM_CLEAR;
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_write_wrapper(rtc_dd,&ctrl_reg,=
 rtc_dd->rtc_base +
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
 =C2=A0 =C2=A0 =C2=A0 PM8XXX_ALARM_CTRL_OFFSET,
>> 1);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00)
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(rtc_dd->r=
tc_dev, "PM8xxx write failed!\n");
>> +
>> +rtc_alarm_handled:
>> + =C2=A0 =C2=A0 =C2=A0 return IRQ_HANDLED;
>> +}
>> +
>> +static int __devinit pm8xxx_rtc_probe(struct platform_device *pdev)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 int rc;
>> + =C2=A0 =C2=A0 =C2=A0 u8 ctrl_reg;
>> + =C2=A0 =C2=A0 =C2=A0 bool rtc_write_enable =3D false;
>> + =C2=A0 =C2=A0 =C2=A0 struct pm8xxx_rtc *rtc_dd;
>> + =C2=A0 =C2=A0 =C2=A0 struct resource *rtc_resource;
>> + =C2=A0 =C2=A0 =C2=A0 const struct pm8xxx_rtc_platform_data *pdata =
=3D mfd_get_data(pdev);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 if (pdata !=3D NULL)
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rtc_write_enable =
=3D pdata->rtc_write_enable;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd =3D kzalloc(sizeof(*rtc_dd), GFP_KERNE=
L);
>> + =C2=A0 =C2=A0 =C2=A0 if (rtc_dd =3D=3D NULL) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(&pdev->de=
v, "Unable to allocate memory!\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return -ENOMEM;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /* Initialise spinlock to protect RTC cntrol =
register */
>> + =C2=A0 =C2=A0 =C2=A0 spin_lock_init(&rtc_dd->ctrl_reg_lock);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->rtc_alarm_irq =3D platform_get_irq(pd=
ev, 0);
>> + =C2=A0 =C2=A0 =C2=A0 if (rtc_dd->rtc_alarm_irq< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(&pdev->de=
v, "Alarm IRQ resource absent!\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc =3D -ENXIO;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto fail_rtc_ena=
ble;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_resource =3D platform_get_resource_byname=
(pdev, IORESOURCE_IO,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 "pmic_rtc_base");
>> + =C2=A0 =C2=A0 =C2=A0 if (!(rtc_resource&& =C2=A0rtc_resource->star=
t)) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(&pdev->de=
v, "RTC IO resource absent!\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc =3D -ENXIO;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto fail_rtc_ena=
ble;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->rtc_base =3D rtc_resource->start;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /* Setup RTC register addresses */
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->rtc_write_base =3D rtc_dd->rtc_base +
>> PM8XXX_RTC_WRITE_OFFSET;
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->rtc_read_base =3D rtc_dd->rtc_base + =
PM8XXX_RTC_READ_OFFSET;
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->alarm_rw_base =3D rtc_dd->rtc_base + =
PM8XXX_ALARM_RW_OFFSET;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->rtc_dev =3D&(pdev->dev);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /* Check if the RTC is on, else turn it on */
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_read_wrapper(rtc_dd,&ctrl_reg, =
rtc_dd->rtc_base, 1);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(&pdev->de=
v, "PM8xxx read failed!\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto fail_rtc_ena=
ble;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 if (!(ctrl_reg& =C2=A0PM8xxx_RTC_ENABLE)) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ctrl_reg |=3D PM8=
xxx_RTC_ENABLE;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc =3D pm8xxx_wri=
te_wrapper(rtc_dd,&ctrl_reg,
>> rtc_dd->rtc_base,
>> +
>> 1);
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) =
{
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 dev_err(&pdev->dev, "PM8xxx write failed!\n");
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 goto fail_rtc_enable;
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->ctrl_reg =3D ctrl_reg;
>> + =C2=A0 =C2=A0 =C2=A0 if (rtc_write_enable =3D=3D true)
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 pm8xxx_rtc_ops.se=
t_time =3D pm8xxx_rtc_set_time;
>> +
>> + =C2=A0 =C2=A0 =C2=A0 platform_set_drvdata(pdev, rtc_dd);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /* Register the RTC device */
>> + =C2=A0 =C2=A0 =C2=A0 rtc_dd->rtc =3D rtc_device_register("pm8xxx_r=
tc",&pdev->dev,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &pm8xxx_rtc_ops, THIS_MODULE);
>> + =C2=A0 =C2=A0 =C2=A0 if (IS_ERR(rtc_dd->rtc)) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(&pdev->de=
v, "%s: RTC registration failed (%ld)\n",
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 __fu=
nc__, PTR_ERR(rtc_dd->rtc));
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rc =3D PTR_ERR(rt=
c_dd->rtc);
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto fail_rtc_ena=
ble;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 /* Request the alarm IRQ */
>> + =C2=A0 =C2=A0 =C2=A0 rc =3D request_any_context_irq(rtc_dd->rtc_al=
arm_irq,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pm8xxx_alarm_trigger,
>> IRQF_TRIGGER_RISING,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"pm8xxx_rtc_alarm", rtc_dd=
);
>> + =C2=A0 =C2=A0 =C2=A0 if (rc< =C2=A00) {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(&pdev->de=
v, "Request IRQ failed (%d)\n", rc);
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 goto fail_req_irq=
;
>> + =C2=A0 =C2=A0 =C2=A0 }
>> +
>> + =C2=A0 =C2=A0 =C2=A0 device_init_wakeup(&pdev->dev, 1);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 dev_dbg(&pdev->dev, "Probe success !!\n");
>> +
>> + =C2=A0 =C2=A0 =C2=A0 return 0;
>> +
>> +fail_req_irq:
>> + =C2=A0 =C2=A0 =C2=A0 rtc_device_unregister(rtc_dd->rtc);
>> +fail_rtc_enable:
>> + =C2=A0 =C2=A0 =C2=A0 platform_set_drvdata(pdev, NULL);
>> + =C2=A0 =C2=A0 =C2=A0 kfree(rtc_dd);
>> + =C2=A0 =C2=A0 =C2=A0 return rc;
>> +}
>> +
>> +#ifdef CONFIG_PM
>> +static int pm8xxx_rtc_resume(struct device *dev)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 struct pm8xxx_rtc *rtc_dd =3D dev_get_drvdata=
(dev);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 if (device_may_wakeup(dev))
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 disable_irq_wake(=
rtc_dd->rtc_alarm_irq);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 return 0;
>> +}
>> +
>> +static int pm8xxx_rtc_suspend(struct device *dev)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 struct pm8xxx_rtc *rtc_dd =3D dev_get_drvdata=
(dev);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 if (device_may_wakeup(dev))
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 enable_irq_wake(r=
tc_dd->rtc_alarm_irq);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 return 0;
>> +}
>> +
>> +static const struct dev_pm_ops pm8xxx_rtc_pm_ops =3D {
>> + =C2=A0 =C2=A0 =C2=A0 .suspend =3D pm8xxx_rtc_suspend,
>> + =C2=A0 =C2=A0 =C2=A0 .resume =3D pm8xxx_rtc_resume,
>> +};
>> +#endif
>> +static int __devexit pm8xxx_rtc_remove(struct platform_device *pdev=
)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 struct pm8xxx_rtc *rtc_dd =3D platform_get_dr=
vdata(pdev);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 device_init_wakeup(&pdev->dev, 0);
>> + =C2=A0 =C2=A0 =C2=A0 free_irq(rtc_dd->rtc_alarm_irq, rtc_dd);
>> + =C2=A0 =C2=A0 =C2=A0 rtc_device_unregister(rtc_dd->rtc);
>> + =C2=A0 =C2=A0 =C2=A0 platform_set_drvdata(pdev, NULL);
>> + =C2=A0 =C2=A0 =C2=A0 kfree(rtc_dd);
>> +
>> + =C2=A0 =C2=A0 =C2=A0 return 0;
>> +}
>> +
>> +static struct platform_driver pm8xxx_rtc_driver =3D {
>> + =C2=A0 =C2=A0 =C2=A0 .probe =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=3D =
pm8xxx_rtc_probe,
>> + =C2=A0 =C2=A0 =C2=A0 .remove =C2=A0 =C2=A0 =C2=A0 =C2=A0 =3D __dev=
exit_p(pm8xxx_rtc_remove),
>> + =C2=A0 =C2=A0 =C2=A0 .driver =3D {
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .name =C2=A0 =3D =
PM8XXX_RTC_DEV_NAME,
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .owner =C2=A0=3D =
THIS_MODULE,
>> +#ifdef CONFIG_PM
>> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 .pm =C2=A0 =C2=A0=
 =3D&pm8xxx_rtc_pm_ops,
>> +#endif
>> + =C2=A0 =C2=A0 =C2=A0 },
>> +};
>> +
>> +static int __init pm8xxx_rtc_init(void)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 return platform_driver_register(&pm8xxx_rtc_d=
river);
>> +}
>> +module_init(pm8xxx_rtc_init);
>> +
>> +static void __exit pm8xxx_rtc_exit(void)
>> +{
>> + =C2=A0 =C2=A0 =C2=A0 platform_driver_unregister(&pm8xxx_rtc_driver=
);
>> +}
>> +module_exit(pm8xxx_rtc_exit);
>> +
>> +MODULE_ALIAS("platform:rtc-pm8xxx");
>> +MODULE_DESCRIPTION("PMIC8xxx RTC driver");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_AUTHOR("Anirudh Ghayal<aghayal@codeaurora.org>");
>> diff --git a/include/linux/mfd/pm8xxx/rtc.h
>> b/include/linux/mfd/pm8xxx/rtc.h
>> new file mode 100644
>> index 0000000..14f1983
>> --- /dev/null
>> +++ b/include/linux/mfd/pm8xxx/rtc.h
>> @@ -0,0 +1,25 @@
>> +/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or mo=
dify
>> + * it under the terms of the GNU General Public License version 2 a=
nd
>> + * only version 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. =C2=A0See t=
he
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#ifndef __RTC_PM8XXX_H__
>> +#define __RTC_PM8XXX_H__
>> +
>> +#define PM8XXX_RTC_DEV_NAME =C2=A0 =C2=A0 "rtc-pm8xxx"
>> +/**
>> + * struct pm8xxx_rtc_pdata - RTC driver platform data
>> + * @rtc_write_enable: variable stating RTC write capability
>> + */
>> +struct pm8xxx_rtc_platform_data {
>> + =C2=A0 =C2=A0 =C2=A0 bool rtc_write_enable;
>> +};
>> +
>> +#endif /* __RTC_PM8XXX_H__ */
>
>



--=20
Wan ZongShun.
www.mcuos.com