From: Linus Walleij <linus.walleij@linaro.org>
To: Stephen Boyd <swboyd@chromium.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
linux-arm-msm@vger.kernel.org,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Doug Anderson <dianders@chromium.org>
Subject: Re: [PATCH] pinctrl: qcom: spmi-mpp: Fix drive strength setting
Date: Mon, 10 Sep 2018 09:31:47 +0200 [thread overview]
Message-ID: <CACRpkdY74znEYMsjAWMn_Erj9KZGzy0DAjRm2FJuFJjEr3HBQg@mail.gmail.com> (raw)
In-Reply-To: <20180831005852.156465-1-swboyd@chromium.org>
On Fri, Aug 31, 2018 at 2:58 AM Stephen Boyd <swboyd@chromium.org> wrote:
> It looks like we parse the drive strength setting here, but never
> actually write it into the hardware to update it. Parse the setting and
> then write it at the end of the pinconf setting function so that it
> actually sticks in the hardware.
>
> Fixes: 0e948042c420 ("pinctrl: qcom: spmi-mpp: Implement support for sink mode")
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Doug Anderson <dianders@chromium.org>
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Patch applied with Bjorn's ACK.
Yours,
Linus Walleij
prev parent reply other threads:[~2018-09-10 7:31 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-31 0:58 [PATCH] pinctrl: qcom: spmi-mpp: Fix drive strength setting Stephen Boyd
2018-09-03 20:58 ` Bjorn Andersson
2018-09-10 7:31 ` Linus Walleij [this message]
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