From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFE92C77B7C for ; Thu, 4 May 2023 18:08:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229887AbjEDSIP (ORCPT ); Thu, 4 May 2023 14:08:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229459AbjEDSIO (ORCPT ); Thu, 4 May 2023 14:08:14 -0400 Received: from mail-oo1-xc34.google.com (mail-oo1-xc34.google.com [IPv6:2607:f8b0:4864:20::c34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E02459E0; Thu, 4 May 2023 11:08:13 -0700 (PDT) Received: by mail-oo1-xc34.google.com with SMTP id 006d021491bc7-547303fccefso535870eaf.3; Thu, 04 May 2023 11:08:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683223693; x=1685815693; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=xo9ZPKfjYHt2qv3p5XYXld4Ww9M7Eu/gP5wGsS4ugts=; b=WmWVKQdJ4kXpxuDVsTGYJXirxdfh0MpwgYxg+cJIDorj84aAA747e+u5D02g/tlCQJ SElVskW438vl4UQIDmOst73rTFpI6dukamAMyZfOFCVfCfWHSED3VoKWCgNYZ49lTtO6 2vRE/TW7REDJB5NkIQDU99BqdP4lnY4qOoXuxmGL7DrsQOL+ybYLS0PRb5S+bJcKowPe sPdZrz8oEgGBJBfJ8YmhdWJl6G/eUC36Y1RhrPXpQqcNYHOxWTk0l8zykCqqI+kaKJ6B ap1+/HEzMtarpW50cILkegl3hIBqblIdTmz9Hl9tGAzI9JXiGOM74LV8in25vIYVoCim 650g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683223693; x=1685815693; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xo9ZPKfjYHt2qv3p5XYXld4Ww9M7Eu/gP5wGsS4ugts=; b=PMgF3vk7/TNDay5P0kFsD+YNm2i22uyCBlOp9qgJqsU/0iUM1aMSDsh1K1Pq+SZrN0 MuKeTT1rvEqdKRp+NI5fsdWIUGDCUwb2hEsMEiWRiVzjkCRNzts8T8Fozwv7ZGWXuNJr AbCs49md3rboRJeNcx0AGuRwtQcHmMtBiH7Dio6kGT6m6woHPo1yM6qh4aD+GjAGthrD ejE1Vmm1FSRZKHmvGYrAdCAVDVKkFO7QB84k1k5oOHYktdjMVPKvMYypFqybnjfbDjlw CvQI6EfKbfhdO48pS8DPSuyUWz6lrZq4Z6E49+tMO/yB0A0mYyJrJquyUzFC0yJ0qeft gmjw== X-Gm-Message-State: AC+VfDw7nSm2OH+ZncNKPd/BTNN1cpawtbVAZA2K42SdJY8Ca/LPrr+O t+RMlzIS8F79MjLVj5APmfimmGu9eLCdiy5bpAY= X-Google-Smtp-Source: ACHHUZ4smDg5nxeRyL73RnMQ8tHc04rAiW534zEE+316+lYeXbVloHvMH7EZuHxsav+tuJowLyvhOsb4Mtk9aeLP8cM= X-Received: by 2002:a4a:d88c:0:b0:538:57d4:2d62 with SMTP id b12-20020a4ad88c000000b0053857d42d62mr12002690oov.2.1683223692626; Thu, 04 May 2023 11:08:12 -0700 (PDT) MIME-Version: 1.0 References: <20230502160950.1758826-1-robdclark@gmail.com> In-Reply-To: From: Rob Clark Date: Thu, 4 May 2023 11:08:02 -0700 Message-ID: Subject: Re: [PATCH 1/2] iommu/arm-smmu-qcom: Fix missing adreno_smmu's To: Konrad Dybcio Cc: dri-devel@lists.freedesktop.org, iommu@lists.linux-foundation.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Sai Prakash Ranjan , Bjorn Andersson , Marijn Suijten , "moderated list:ARM SMMU DRIVERS" , "open list:IOMMU SUBSYSTEM" , open list Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, May 4, 2023 at 10:41=E2=80=AFAM Konrad Dybcio wrote: > > > > On 2.05.2023 18:09, Rob Clark wrote: > > From: Rob Clark > > > > When the special handling of qcom,adreno-smmu was moved into > > qcom_smmu_create(), it was overlooked that we didn't have all the > > required entries in qcom_smmu_impl_of_match. So we stopped getting > > adreno_smmu_priv on sc7180, breaking per-process pgtables. > > > > Fixes: 30b912a03d91 ("iommu/arm-smmu-qcom: Move the qcom,adreno-smmu ch= eck into qcom_smmu_create") > > Signed-off-by: Rob Clark > > --- > I believe the issue here is the lack of qcom,sc7180-smmu-v2 instead. > > qcom,adreno-smmu does not have to imply the "qcom smmu v2" impl Yes, but the ordering after "qcom,smmu-500" does. Currently we just need the one missing "qcom,sc7180-smmu-v2" but that seemed kind of fragile to me, which is why I went with "qcom,adreno-smmu" as a catch-all BR, -R > > Konrad > > drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 5 +++++ > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu= /arm/arm-smmu/arm-smmu-qcom.c > > index d1b296b95c86..88c89424485b 100644 > > --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > > +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c > > @@ -512,20 +512,25 @@ static const struct of_device_id __maybe_unused q= com_smmu_impl_of_match[] =3D { > > { .compatible =3D "qcom,sm6115-smmu-500", .data =3D &qcom_smmu_50= 0_impl0_data}, > > { .compatible =3D "qcom,sm6125-smmu-500", .data =3D &qcom_smmu_50= 0_impl0_data }, > > { .compatible =3D "qcom,sm6350-smmu-v2", .data =3D &qcom_smmu_v2_= data }, > > { .compatible =3D "qcom,sm6350-smmu-500", .data =3D &qcom_smmu_50= 0_impl0_data }, > > { .compatible =3D "qcom,sm6375-smmu-500", .data =3D &qcom_smmu_50= 0_impl0_data }, > > { .compatible =3D "qcom,sm8150-smmu-500", .data =3D &qcom_smmu_50= 0_impl0_data }, > > { .compatible =3D "qcom,sm8250-smmu-500", .data =3D &qcom_smmu_50= 0_impl0_data }, > > { .compatible =3D "qcom,sm8350-smmu-500", .data =3D &qcom_smmu_50= 0_impl0_data }, > > { .compatible =3D "qcom,sm8450-smmu-500", .data =3D &qcom_smmu_50= 0_impl0_data }, > > { .compatible =3D "qcom,smmu-500", .data =3D &qcom_smmu_500_impl0= _data }, > > + /* > > + * Should come after the qcom,smmu-500 fallback so smmu-500 varia= nts of > > + * adreno-smmu get qcom_adreno_smmu_500_impl: > > + */ > > + { .compatible =3D "qcom,adreno-smmu", .data =3D &qcom_smmu_v2_dat= a }, > > { } > > }; > > > > #ifdef CONFIG_ACPI > > static struct acpi_platform_list qcom_acpi_platlist[] =3D { > > { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU"= }, > > { "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, "QCOM SMMU"= }, > > { } > > }; > > #endif