Re: [PATCH 3/3] ARM64: DT: add iommu for msm8916

[Rob Clark <robdclark@gmail.com>]

On Tue, May 30, 2017 at 8:14 PM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 05/25, Rob Clark wrote:
>> +             apps_iommu: iommu@1ef0000 {
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     #iommu-cells = <1>;
>> +                     compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
>> +                     ranges = <0 0x1e20000 0x40000>;
>> +                     reg = <0x1ef0000 0x3000>;
>> +                     clocks = <&gcc GCC_SMMU_CFG_CLK>,
>> +                              <&gcc GCC_APSS_TCU_CLK>;
>> +                     clock-names = "iface", "bus";
>> +                     qcom,iommu-secure-id = <17>;
>> +
>> +                     // mdp_0:
>> +                     iommu-ctx@4000 {
>> +                             compatible = "qcom,msm-iommu-v1-ns";
>> +                             reg = <0x4000 0x1000>;
>> +                             interrupts = <GIC_SPI 70 0>;
>
> s/0/IRQ_TYPE_LEVEL_HIGH/

0 actually seems to be _NONE.. so using _HIGH would change how irq is
configured (according to gic_configure_irq()).  Do you expect that to
work?  I'm probably going based on what was in downstream dt, and some
of that is more a pain to retest so I'd rather not change the type
unless at least one of us knows what they are doing.

>> +                     };
>> +
>> +                     // venus_ns:
>> +                     iommu-ctx@5000 {
>> +                             compatible = "qcom,msm-iommu-v1-sec";
>> +                             reg = <0x5000 0x1000>;
>> +                             interrupts = <GIC_SPI 70 0>;
>
> s/0/IRQ_TYPE_LEVEL_HIGH/
>
> Is it the same interrupt number (70) twice? Not 71 or something?

According to downstream.  Not *entirely* sure how that is supposed to
work as far as dispatching fault callback to the right driver, but at
least unlike with the gpu, if we get a fault for mdp, that is entirely
the kernels fault.  So meh?

If you know better, let me know.

BR,
-R

>
>> +                     };
>> +             };
>> +
>> +             gpu_iommu: iommu@1f08000 {
>> +                     #address-cells = <1>;
>> +                     #size-cells = <1>;
>> +                     #iommu-cells = <1>;
>> +                     compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
>> +                     ranges = <0 0x1f08000 0x10000>;
>> +                     clocks = <&gcc GCC_SMMU_CFG_CLK>,
>> +                              <&gcc GCC_GFX_TCU_CLK>;
>> +                     clock-names = "iface", "bus";
>> +                     qcom,iommu-secure-id = <18>;
>> +
>> +                     // gfx3d_user:
>> +                     iommu-ctx@1000 {
>> +                             compatible = "qcom,msm-iommu-v1-ns";
>> +                             reg = <0x1000 0x1000>;
>> +                             interrupts = <GIC_SPI 241 0>;
>
> s/0/IRQ_TYPE_LEVEL_HIGH/
>
>> +                     };
>> +
>> +                     // gfx3d_priv:
>> +                     iommu-ctx@2000 {
>> +                             compatible = "qcom,msm-iommu-v1-ns";
>> +                             reg = <0x2000 0x1000>;
>> +                             interrupts = <GIC_SPI 242 0>;
>
> s/0/IRQ_TYPE_LEVEL_HIGH/
>
>> +                     };
>> +             };
>> +
>>               gpu_opp_table: opp_table {
>>                       compatible = "operating-points-v2";
>>
>
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