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Wed, 28 Sep 2022 10:36:46 -0700 (PDT) Received: from [127.0.0.1] ([94.25.229.4]) by smtp.gmail.com with ESMTPSA id o27-20020ac25e3b000000b0049464d89e40sm529972lfg.72.2022.09.28.10.36.45 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Sep 2022 10:36:46 -0700 (PDT) Date: Wed, 28 Sep 2022 20:34:37 +0300 From: Dmitry Baryshkov To: Johan Hovold , Vinod Koul CC: Andy Gross , Bjorn Andersson , Konrad Dybcio , Kishon Vijay Abraham I , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 04/13] phy: qcom-qmp-pcie: unify ipq registers User-Agent: K-9 Mail for Android In-Reply-To: <20220928152822.30687-5-johan+linaro@kernel.org> References: <20220928152822.30687-1-johan+linaro@kernel.org> <20220928152822.30687-5-johan+linaro@kernel.org> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 28 September 2022 18:28:13 GMT+03:00, Johan Hovold wrote: >The IPQ register array is identical to sm8250_pcie_regs_layout so drop >the former=2E I'd not do such merge=2E They belong to different generations=2E I'd sugge= st changing these arrays to use symbolic names defined in corresponding qmp= headers=2E > >Signed-off-by: Johan Hovold >--- > drivers/phy/qualcomm/phy-qcom-qmp-pcie=2Ec | 11 ++--------- > 1 file changed, 2 insertions(+), 9 deletions(-) > >diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie=2Ec b/drivers/phy/qua= lcomm/phy-qcom-qmp-pcie=2Ec >index ec453f908f1d=2E=2E7b3f7e42edd5 100644 >--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie=2Ec >+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie=2Ec >@@ -86,13 +86,6 @@ enum qphy_reg_layout { > QPHY_LAYOUT_SIZE > }; >=20 >-static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE]= =3D { >- [QPHY_SW_RESET] =3D 0x00, >- [QPHY_START_CTRL] =3D 0x44, >- [QPHY_PCS_STATUS] =3D 0x14, >- [QPHY_PCS_POWER_DOWN_CONTROL] =3D 0x40, >-}; >- > static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] =3D { > [QPHY_SW_RESET] =3D 0x00, > [QPHY_START_CTRL] =3D 0x08, >@@ -1492,7 +1485,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen= 3_cfg =3D { > =2Enum_resets =3D ARRAY_SIZE(ipq8074_pciephy_reset_l), > =2Evreg_list =3D NULL, > =2Enum_vregs =3D 0, >- =2Eregs =3D ipq_pciephy_gen3_regs_layout, >+ =2Eregs =3D sm8250_pcie_regs_layout, >=20 > =2Estart_ctrl =3D SERDES_START | PCS_START, > =2Epwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, >@@ -1523,7 +1516,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg= =3D { > =2Enum_resets =3D ARRAY_SIZE(ipq8074_pciephy_reset_l), > =2Evreg_list =3D NULL, > =2Enum_vregs =3D 0, >- =2Eregs =3D ipq_pciephy_gen3_regs_layout, >+ =2Eregs =3D sm8250_pcie_regs_layout, >=20 > =2Estart_ctrl =3D SERDES_START | PCS_START, > =2Epwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, --=20 With best wishes Dmitry