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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id p35-20020a056402502300b00463b9d47e1fsm1805512eda.71.2022.11.25.06.12.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Nov 2022 06:12:25 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 25 Nov 2022 15:12:24 +0100 Message-Id: To: "Johan Hovold" Cc: , <~postmarketos/upstreaming@lists.sr.ht>, , "Andy Gross" , "Bjorn Andersson" , "Konrad Dybcio" , "Vinod Koul" , "Kishon Vijay Abraham I" , "Rob Herring" , "Krzysztof Kozlowski" , , , Subject: Re: [RFC PATCH v2 1/3] dt-bindings: phy: qcom,qmp-usb3-dp: Add sm6350 compatible From: "Luca Weiss" X-Mailer: aerc 0.13.0 References: <20221125092749.46073-1-luca.weiss@fairphone.com> In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri Nov 25, 2022 at 2:52 PM CET, Johan Hovold wrote: > On Fri, Nov 25, 2022 at 01:53:25PM +0100, Luca Weiss wrote: > > > Parent clocks (ref_clk_src) should not be included in the binding, bu= t > > > rather be handled by the clock driver. For example, see: > > > > > > https://lore.kernel.org/all/20221121085058.31213-4-johan+linaro@kern= el.org/ > > > https://lore.kernel.org/all/20221115152956.21677-1-quic_shazhuss@qui= cinc.com/ > >=20 > > So I assume you mean that I shouldn't do this: > >=20 > > clocks =3D <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > > <&rpmhcc RPMH_QLINK_CLK>, > > <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > > <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > > clock-names =3D "aux", "ref", "com_aux", "usb3_pipe"; > >=20 > > But for "ref" use GCC_USB3_PRIM_CLKREF_CLK? That also seems to work > > fine, also if RPMH_QLINK_CLK is not used from Linux-side (checked in > > debugfs). > > Exactly. Since the vendor dts describes RPMH_QLINK_CLK as parent of ref, > I'd suggest modelling that in the clock driver. Perhaps it has just been > left on by the boot firmware. Someone with access to docs may be able > explain how it is supposed to be used. RPMH_QLINK_CLK is also in msm-4.19 ref_clk_src for GCC_UFS_MEM_CLKREF_CLK (ufsphy_mem) and also ref_clk (ufshc_mem). Honestly since it works fine without adding this to gcc driver and I don't really know much about clk (and have no docs for this) would it be okay to just ignore RPMH_QLINK_CLK? > > > And for the driver patch, I've discovered that this phy doesn't have > > separate txa/tbx region, so dts was also wrong there. Do you know if > > there's a way to test DP phy initialization without having all the USB-= C > > plumbing in place? Might be good to validate at least phy init works if > > we're already touching all of this. > > Do you mean that it appears to work as sc8280xp with txa/txb shared by > both the USB and DP parts? Yes, looks like it. Can't find any evidence pointing in any other direction at least, everything I've seen shows .txa =3D 0x1200 & .txb =3D 0x1600. > > I guess you need a proper setup to test it properly. Not sure what > you'll be able to learn otherwise, apart from whether it passes basic > smoke testing. Currently it's not even smoke testing because dp phy is never getting enabled because there's no consumer. That's why I guess it was never noticed it's wrongly described in dts. Regards Luca > > Johan