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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 13-20020a170906300d00b00741a251d9e8sm3487278ejz.171.2022.12.12.07.53.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Dec 2022 07:53:49 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 12 Dec 2022 16:53:49 +0100 Message-Id: Cc: , , , , , , , , Subject: Re: [PATCH v2 13/13] qcom: llcc/edac: Support polling mode for ECC handling From: "Luca Weiss" To: "Manivannan Sadhasivam" , , , , , X-Mailer: aerc 0.13.0 References: <20221212123311.146261-1-manivannan.sadhasivam@linaro.org> <20221212123311.146261-14-manivannan.sadhasivam@linaro.org> In-Reply-To: <20221212123311.146261-14-manivannan.sadhasivam@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi Manivannan, On Mon Dec 12, 2022 at 1:33 PM CET, Manivannan Sadhasivam wrote: > Not all Qcom platforms support IRQ mode for ECC handling. For those > platforms, the current EDAC driver will not be probed due to missing ECC > IRQ in devicetree. > > So add support for polling mode so that the EDAC driver can be used on al= l > Qcom platforms supporting LLCC. > > The polling delay of 5000ms is chosed based on Qcom downstream/vendor > driver. I think it does work for me on SM6350, I get this in dmesg: [ 0.054608] EDAC MC: Ver: 3.0.0 [ 0.273913] EDAC DEVICE0: Giving out device to module qcom_llcc_edac con= troller llcc: DEV qcom_llcc_edac (POLLED) What I've noticed though is that the 5000ms poll you defined in the driver doesn't seem to be reflected at runtime? Or am I looking at different things? / # cat /sys/devices/system/edac/qcom-llcc/poll_msec=20 1000 Regards Luca > > Reported-by: Luca Weiss > Signed-off-by: Manivannan Sadhasivam > --- > drivers/edac/qcom_edac.c | 37 +++++++++++++++++++++++++----------- > drivers/soc/qcom/llcc-qcom.c | 13 ++++++------- > 2 files changed, 32 insertions(+), 18 deletions(-) > > diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c > index 5be93577fc03..f7afb5375293 100644 > --- a/drivers/edac/qcom_edac.c > +++ b/drivers/edac/qcom_edac.c > @@ -76,6 +76,8 @@ > #define DRP0_INTERRUPT_ENABLE BIT(6) > #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 > =20 > +#define ECC_POLL_MSEC 5000 > + > enum { > LLCC_DRAM_CE =3D 0, > LLCC_DRAM_UE, > @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, i= nt err_type, u32 bank) > return ret; > } > =20 > -static irqreturn_t > -llcc_ecc_irq_handler(int irq, void *edev_ctl) > +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) > { > struct edac_device_ctl_info *edac_dev_ctl =3D edev_ctl; > struct llcc_drv_data *drv =3D edac_dev_ctl->pvt_info; > @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) > return irq_rc; > } > =20 > +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) > +{ > + llcc_ecc_irq_handler(0, edev_ctl); > +} > + > static int qcom_llcc_edac_probe(struct platform_device *pdev) > { > struct llcc_drv_data *llcc_driv_data =3D pdev->dev.platform_data; > @@ -356,22 +362,31 @@ static int qcom_llcc_edac_probe(struct platform_dev= ice *pdev) > edev_ctl->panic_on_ue =3D LLCC_ERP_PANIC_ON_UE; > edev_ctl->pvt_info =3D llcc_driv_data; > =20 > + /* Check if LLCC driver has passed ECC IRQ */ > + ecc_irq =3D llcc_driv_data->ecc_irq; > + if (ecc_irq > 0) { > + /* Use interrupt mode if IRQ is available */ > + edac_op_state =3D EDAC_OPSTATE_INT; > + } else { > + /* Fall back to polling mode otherwise */ > + edac_op_state =3D EDAC_OPSTATE_POLL; > + edev_ctl->poll_msec =3D ECC_POLL_MSEC; > + edev_ctl->edac_check =3D llcc_ecc_check; > + } > + > rc =3D edac_device_add_device(edev_ctl); > if (rc) > goto out_mem; > =20 > platform_set_drvdata(pdev, edev_ctl); > =20 > - /* Request for ecc irq */ > - ecc_irq =3D llcc_driv_data->ecc_irq; > - if (ecc_irq < 0) { > - rc =3D -ENODEV; > - goto out_dev; > - } > - rc =3D devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, > + /* Request ECC IRQ if available */ > + if (ecc_irq > 0) { > + rc =3D devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, > IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); > - if (rc) > - goto out_dev; > + if (rc) > + goto out_dev; > + } > =20 > return rc; > =20 > diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c > index a29f22dad7fa..e044e6756415 100644 > --- a/drivers/soc/qcom/llcc-qcom.c > +++ b/drivers/soc/qcom/llcc-qcom.c > @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device= *pdev) > goto err; > =20 > drv_data->ecc_irq =3D platform_get_irq_optional(pdev, 0); > - if (drv_data->ecc_irq >=3D 0) { > - llcc_edac =3D platform_device_register_data(&pdev->dev, > - "qcom_llcc_edac", -1, drv_data, > - sizeof(*drv_data)); > - if (IS_ERR(llcc_edac)) > - dev_err(dev, "Failed to register llcc edac driver\n"); > - } > + > + llcc_edac =3D platform_device_register_data(&pdev->dev, > + "qcom_llcc_edac", -1, drv_data, > + sizeof(*drv_data)); > + if (IS_ERR(llcc_edac)) > + dev_err(dev, "Failed to register llcc edac driver\n"); > =20 > return 0; > err: > --=20 > 2.25.1