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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id o6-20020a17090611c600b009ad875d12d7sm1149455eja.210.2023.10.05.06.01.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Oct 2023 06:01:23 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Thu, 05 Oct 2023 15:01:22 +0200 Message-Id: Cc: , , , Subject: Re: [PATCH V4 2/4] arm64: dts: qcom: sc7280: Add UFS nodes for sc7280 soc From: "Luca Weiss" To: "Nitin Rawat" , , , , , , , , , , , X-Mailer: aerc 0.15.2 References: <20230929131936.29421-1-quic_nitirawa@quicinc.com> <20230929131936.29421-3-quic_nitirawa@quicinc.com> In-Reply-To: <20230929131936.29421-3-quic_nitirawa@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Fri Sep 29, 2023 at 3:19 PM CEST, Nitin Rawat wrote: > Add UFS host controller and PHY nodes for sc7280 soc. Hi Nitin, I left some comments for v3 that maybe you missed before sending v4: https://lore.kernel.org/linux-arm-msm/CVVA1OVF4W9E.380D6QC1K9GD6@otso/ At least the clock part should definitely be fixed, ICE we can do later. Regards Luca > > Signed-off-by: Nitin Rawat > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 66 ++++++++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/q= com/sc7280.dtsi > index 66f1eb83cca7..163e3df60966 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -3353,6 +3353,72 @@ > }; > }; > > + ufs_mem_hc: ufs@1d84000 { > + compatible =3D "qcom,sc7280-ufshc", "qcom,ufshc", > + "jedec,ufs-2.0"; > + reg =3D <0x0 0x01d84000 0x0 0x3000>; > + interrupts =3D ; > + phys =3D <&ufs_mem_phy>; > + phy-names =3D "ufsphy"; > + lanes-per-direction =3D <2>; > + #reset-cells =3D <1>; > + resets =3D <&gcc GCC_UFS_PHY_BCR>; > + reset-names =3D "rst"; > + > + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; > + required-opps =3D <&rpmhpd_opp_nom>; > + > + iommus =3D <&apps_smmu 0x80 0x0>; > + dma-coherent; > + > + interconnects =3D <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0= >, > + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_UFS_MEM_CFG 0>; > + > + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + clock-names =3D "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > + freq-table-hz =3D > + <75000000 300000000>, > + <0 0>, > + <0 0>, > + <75000000 300000000>, > + <0 0>, > + <0 0>, > + <0 0>, > + <0 0>; > + status =3D "disabled"; > + }; > + > + ufs_mem_phy: phy@1d87000 { > + compatible =3D "qcom,sc7280-qmp-ufs-phy"; > + reg =3D <0x0 0x01d87000 0x0 0xe00>; > + clocks =3D <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, > + <&gcc GCC_UFS_1_CLKREF_EN>; > + clock-names =3D "ref", "ref_aux", "qref"; > + > + resets =3D <&ufs_mem_hc 0>; > + reset-names =3D "ufsphy"; > + > + #clock-cells =3D <1>; > + #phy-cells =3D <0>; > + > + status =3D "disabled"; > + }; > + > usb_1_hsphy: phy@88e3000 { > compatible =3D "qcom,sc7280-usb-hs-phy", > "qcom,usb-snps-hs-7nm-phy"; > -- > 2.17.1