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[62.108.10.64]) by smtp.gmail.com with ESMTPSA id v6-20020a1709067d8600b0099bcf1c07c6sm5660388ejo.138.2023.10.30.02.12.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Oct 2023 02:12:15 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 30 Oct 2023 10:12:14 +0100 Message-Id: Cc: <~postmarketos/upstreaming@lists.sr.ht>, , "Krzysztof Kozlowski" , "Rob Herring" , =?utf-8?q?Matti_Lehtim=C3=A4ki?= , , , , Subject: Re: [PATCH 7/9] arm64: dts: qcom: sc7280: Add CDSP node From: "Luca Weiss" To: "Mukesh Ojha" , "Andy Gross" , "Bjorn Andersson" , "Konrad Dybcio" , "Mathieu Poirier" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Manivannan Sadhasivam" , X-Mailer: aerc 0.15.2 References: <20231027-sc7280-remoteprocs-v1-0-05ce95d9315a@fairphone.com> <20231027-sc7280-remoteprocs-v1-7-05ce95d9315a@fairphone.com> <7934a36a-9438-719a-2ed0-4a78757b044b@quicinc.com> In-Reply-To: <7934a36a-9438-719a-2ed0-4a78757b044b@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Mon Oct 30, 2023 at 10:04 AM CET, Mukesh Ojha wrote: > > > On 10/27/2023 7:50 PM, Luca Weiss wrote: > > Add the node for the ADSP found on the SC7280 SoC, using standard > > Qualcomm firmware. > >=20 > > The memory region for sc7280-chrome-common.dtsi is taken from msm-5.4 > > yupik.dtsi since the other areas also seem to match that file there, > > though I cannot be sure there. > >=20 > > Signed-off-by: Luca Weiss > > --- > > arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi | 5 + > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 138 ++++++++++++= +++++++++ > > 2 files changed, 143 insertions(+) > >=20 > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/= arm64/boot/dts/qcom/sc7280-chrome-common.dtsi > > index eb55616e0892..6e5a9d4c1fda 100644 > > --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi > > @@ -29,6 +29,11 @@ adsp_mem: memory@86700000 { > > no-map; > > }; > > =20 > > + cdsp_mem: memory@88f00000 { > > + reg =3D <0x0 0x88f00000 0x0 0x1e00000>; > > + no-map; > > + }; > > + > > Just a question, why to do it here, if chrome does not use this ? Other memory regions in sc7280.dtsi also get referenced but not actually defined in that file, like mpss_mem and wpss_mem. Alternatively we can also try and solve this differently, but then we should probably also adjust mpss and wpss to be consistent. Apart from either declaring cdsp_mem in sc7280.dtsi or "/delete-property/ memory-region;" for CDSP I don't really have better ideas though. I also imagine these ChromeOS devices will want to enable cdsp at some point but I don't know any plans there. Regards Luca > > -Mukesh > > > camera_mem: memory@8ad00000 { > > reg =3D <0x0 0x8ad00000 0x0 0x500000>; > > no-map; > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts= /qcom/sc7280.dtsi > > index cc153f4e6979..e15646289bf7 100644 > > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > > @@ -3815,6 +3815,144 @@ nsp_noc: interconnect@a0c0000 { > > qcom,bcm-voters =3D <&apps_bcm_voter>; > > }; > > =20 > > + remoteproc_cdsp: remoteproc@a300000 { > > + compatible =3D "qcom,sc7280-cdsp-pas"; > > + reg =3D <0 0x0a300000 0 0x10000>; > > + > > + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, > > + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, > > + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, > > + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, > > + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, > > + <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; > > + interrupt-names =3D "wdog", "fatal", "ready", "handover", > > + "stop-ack", "shutdown-ack"; > > + > > + clocks =3D <&rpmhcc RPMH_CXO_CLK>; > > + clock-names =3D "xo"; > > + > > + power-domains =3D <&rpmhpd SC7280_CX>, > > + <&rpmhpd SC7280_MX>; > > + power-domain-names =3D "cx", "mx"; > > + > > + interconnects =3D <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 = 0>; > > + > > + memory-region =3D <&cdsp_mem>; > > + > > + qcom,qmp =3D <&aoss_qmp>; > > + > > + qcom,smem-states =3D <&cdsp_smp2p_out 0>; > > + qcom,smem-state-names =3D "stop"; > > + > > + status =3D "disabled"; > > + > > + glink-edge { > > + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP > > + IPCC_MPROC_SIGNAL_GLINK_QMP > > + IRQ_TYPE_EDGE_RISING>; > > + mboxes =3D <&ipcc IPCC_CLIENT_CDSP > > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > > + > > + label =3D "cdsp"; > > + qcom,remote-pid =3D <5>; > > + > > + fastrpc { > > + compatible =3D "qcom,fastrpc"; > > + qcom,glink-channels =3D "fastrpcglink-apps-dsp"; > > + label =3D "cdsp"; > > + qcom,non-secure-domain; > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + compute-cb@1 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <1>; > > + iommus =3D <&apps_smmu 0x11a1 0x0420>, > > + <&apps_smmu 0x1181 0x0420>; > > + }; > > + > > + compute-cb@2 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <2>; > > + iommus =3D <&apps_smmu 0x11a2 0x0420>, > > + <&apps_smmu 0x1182 0x0420>; > > + }; > > + > > + compute-cb@3 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <3>; > > + iommus =3D <&apps_smmu 0x11a3 0x0420>, > > + <&apps_smmu 0x1183 0x0420>; > > + }; > > + > > + compute-cb@4 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <4>; > > + iommus =3D <&apps_smmu 0x11a4 0x0420>, > > + <&apps_smmu 0x1184 0x0420>; > > + }; > > + > > + compute-cb@5 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <5>; > > + iommus =3D <&apps_smmu 0x11a5 0x0420>, > > + <&apps_smmu 0x1185 0x0420>; > > + }; > > + > > + compute-cb@6 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <6>; > > + iommus =3D <&apps_smmu 0x11a6 0x0420>, > > + <&apps_smmu 0x1186 0x0420>; > > + }; > > + > > + compute-cb@7 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <7>; > > + iommus =3D <&apps_smmu 0x11a7 0x0420>, > > + <&apps_smmu 0x1187 0x0420>; > > + }; > > + > > + compute-cb@8 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <8>; > > + iommus =3D <&apps_smmu 0x11a8 0x0420>, > > + <&apps_smmu 0x1188 0x0420>; > > + }; > > + > > + /* note: secure cb9 in downstream */ > > + > > + compute-cb@11 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <11>; > > + iommus =3D <&apps_smmu 0x11ab 0x0420>, > > + <&apps_smmu 0x118b 0x0420>; > > + }; > > + > > + compute-cb@12 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <12>; > > + iommus =3D <&apps_smmu 0x11ac 0x0420>, > > + <&apps_smmu 0x118c 0x0420>; > > + }; > > + > > + compute-cb@13 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <13>; > > + iommus =3D <&apps_smmu 0x11ad 0x0420>, > > + <&apps_smmu 0x118d 0x0420>; > > + }; > > + > > + compute-cb@14 { > > + compatible =3D "qcom,fastrpc-compute-cb"; > > + reg =3D <14>; > > + iommus =3D <&apps_smmu 0x11ae 0x0420>, > > + <&apps_smmu 0x118e 0x0420>; > > + }; > > + }; > > + }; > > + }; > > + > > usb_1: usb@a6f8800 { > > compatible =3D "qcom,sc7280-dwc3", "qcom,dwc3"; > > reg =3D <0 0x0a6f8800 0 0x400>; > >=20