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[46.125.249.120]) by smtp.gmail.com with ESMTPSA id g14-20020a170906198e00b00a46d049ff63sm114217ejd.21.2024.03.18.03.45.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Mar 2024 03:45:59 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 18 Mar 2024 11:45:57 +0100 Message-Id: Cc: "Konrad Dybcio" , "Vinod Koul" , "Kishon Vijay Abraham I" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Abhinav Kumar" , , , , Subject: Re: [PATCH RFT 0/7] arm64: qcom: allow up to 4 lanes for the Type-C DisplayPort Altmode From: "Luca Weiss" To: "Bjorn Andersson" , "Neil Armstrong" X-Mailer: aerc 0.15.2 References: <20240229-topic-sm8x50-upstream-phy-combo-typec-mux-v1-0-07e24a231840@linaro.org> <7a7aa05f-9ae6-4ca0-a423-224fc78fbd0c@linaro.org> In-Reply-To: On Sat Mar 16, 2024 at 5:01 PM CET, Bjorn Andersson wrote: > On Fri, Mar 15, 2024 at 06:35:15PM +0100, Neil Armstrong wrote: > > On 15/03/2024 18:19, Luca Weiss wrote: > > > On Thu Feb 29, 2024 at 2:07 PM CET, Neil Armstrong wrote: > > > > Register a typec mux in order to change the PHY mode on the Type-C > > > > mux events depending on the mode and the svid when in Altmode setup= . > > > >=20 > > > > The DisplayPort phy should be left enabled if is still powered on > > > > by the DRM DisplayPort controller, so bail out until the DisplayPor= t > > > > PHY is not powered off. > > > >=20 > > > > The Type-C Mode/SVID only changes on plug/unplug, and USB SAFE stat= es > > > > will be set in between of USB-Only, Combo and DisplayPort Only so > > > > this will leave enough time to the DRM DisplayPort controller to > > > > turn of the DisplayPort PHY. > > > >=20 > > > > The patchset also includes bindings changes and DT changes. > > > >=20 > > > > This has been successfully tested on an SM8550 board, but the > > > > Thinkpad X13s deserved testing between non-PD USB, non-PD DisplayPo= rt, > > > > PD USB Hubs and PD Altmode Dongles to make sure the switch works > > > > as expected. > > > >=20 > > > > The DisplayPort 4 lanes setup can be check with: > > > > $ cat /sys/kernel/debug/dri/ae01000.display-controller/DP-1/dp_debu= g > > > > name =3D msm_dp > > > > drm_dp_link > > > > rate =3D 540000 > > > > num_lanes =3D 4 > > >=20 > > > Hi Neil, > > >=20 > > > I tried this on QCM6490/SC7280 which should also support 4-lane DP bu= t I > > > haven't had any success so far. > > >=20 > [..] > > > [ 1775.563969] [drm:dp_ctrl_link_train] *ERROR* max v_level reached > > > [ 1775.564031] [drm:dp_ctrl_link_train] *ERROR* link training #1 fail= ed. ret=3D-11 > >=20 > > Interesting #1 means the 4 lanes are not physically connected to the ot= her side, > > perhaps QCM6490/SC7280 requires a specific way to enable the 4 lanes in= the PHY, > > or some fixups in the init tables. > >=20 > > I tested the same on rb3gen2 (qcs6490) a couple of weeks ago, with the > same outcome. Looking at the AUX reads, after switching to 4-lane the > link training is failing on all 4 lanes, in contrast to succeeding only > on the first 2 if you e.g. forget to mux the other two. Good to know it's not just my device then ;) > > As such, my expectation is that there's something wrong in the QMP PHY > (or possibly redriver) for this platform. Since I imagine rb3gen2 uses a different redriver setup compared to FP5, I wouldn't say that's at fault for now? And at least my ptn36502 driver only has very little difference between 2-lane and 4-lane setup, only setting the mode to DP-only and 4-lane (vs USB+DP and 2-lane), nothing else. Regards Luca > > Regards, > Bjorn