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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id fe1-20020a056402390100b005701df2ea98sm3207437edb.32.2024.04.16.04.38.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Apr 2024 04:38:44 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 16 Apr 2024 13:38:43 +0200 Message-Id: To: "Viken Dadhaniya" , , , , , , , , , , , , , Cc: , Subject: Re: [PATCH v1] arm64: dts: qcom: sc7280: Remove CTS/RTS configuration From: "Luca Weiss" X-Mailer: aerc 0.17.0 References: <20240416105650.2626-1-quic_vdadhani@quicinc.com> In-Reply-To: <20240416105650.2626-1-quic_vdadhani@quicinc.com> On Tue Apr 16, 2024 at 12:56 PM CEST, Viken Dadhaniya wrote: > Remove CTS and RTS pinctrl configuration for UART5 node as > it's designed for debug UART for all the board variants of the > sc7280 chipset. > > Also change compatible string to debug UART. This change has little to do with the SoC design though and is dependent on the usage on a given board, right? Also the QCM6490 datasheet mentions gpio21 & gpio22 can be used for UART_CTS and UART_RFR. But at least consistency-wise this change makes sense, in practically all other SoCs one UART is marked as geni-debug-uart. But with this patch you should then also remove some overrides that are placed in various boards already? arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts: compatible =3D "qco= m,geni-debug-uart"; arch/arm64/boot/dts/qcom/qcm6490-idp.dts: compatible =3D "qcom,geni-d= ebug-uart"; arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts: compatible =3D "qcom,geni-d= ebug-uart"; arch/arm64/boot/dts/qcom/sc7280-idp.dtsi: compatible =3D "qcom,geni-d= ebug-uart"; arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi: compatible =3D "qcom,geni-d= ebug-uart"; Regards Luca > > Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT nod= e") > Signed-off-by: Viken Dadhaniya > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------ > 1 file changed, 2 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/q= com/sc7280.dtsi > index 38c183b2bb26..2a6b4c4639d1 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -1440,12 +1440,12 @@ > }; > =20 > uart5: serial@994000 { > - compatible =3D "qcom,geni-uart"; > + compatible =3D "qcom,geni-debug-uart"; > reg =3D <0 0x00994000 0 0x4000>; > clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > clock-names =3D "se"; > pinctrl-names =3D "default"; > - pinctrl-0 =3D <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <= &qup_uart5_rx>; > + pinctrl-0 =3D <&qup_uart5_tx>, <&qup_uart5_rx>; > interrupts =3D ; > power-domains =3D <&rpmhpd SC7280_CX>; > operating-points-v2 =3D <&qup_opp_table>; > @@ -5397,16 +5397,6 @@ > function =3D "qup04"; > }; > =20 > - qup_uart5_cts: qup-uart5-cts-state { > - pins =3D "gpio20"; > - function =3D "qup05"; > - }; > - > - qup_uart5_rts: qup-uart5-rts-state { > - pins =3D "gpio21"; > - function =3D "qup05"; > - }; > - > qup_uart5_tx: qup-uart5-tx-state { > pins =3D "gpio22"; > function =3D "qup05";