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charset=UTF-8 Date: Fri, 06 Dec 2024 08:51:38 +0100 Message-Id: Subject: Re: [PATCH v7 4/5] arm64: dts: qcom: sc7280: Add support for camss From: "Luca Weiss" To: "Vikram Sharma" , , , , , , , , , , , , , , , Cc: , , , , , X-Mailer: aerc 0.18.2-0-ge037c095a049 References: <20241204100003.300123-1-quic_vikramsa@quicinc.com> <20241204100003.300123-5-quic_vikramsa@quicinc.com> In-Reply-To: <20241204100003.300123-5-quic_vikramsa@quicinc.com> On Wed Dec 4, 2024 at 11:00 AM CET, Vikram Sharma wrote: > Add changes to support the camera subsystem on the SC7280. > > Signed-off-by: Suresh Vankadara > Signed-off-by: Trishansh Bhardwaj > Signed-off-by: Vikram Sharma Hi Vikram, This is working on QCM6490 Fairphone 5 smartphone with WIP drivers for IMX858 and S5KJN1, thanks! Tested-by: Luca Weiss # qcm6490-fairphone-fp5 Regards Luca > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 172 +++++++++++++++++++++++++++ > 1 file changed, 172 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/q= com/sc7280.dtsi > index 55db1c83ef55..e363996602d6 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -4426,6 +4426,178 @@ cci1_i2c1: i2c-bus@1 { > }; > }; > =20 > + camss: camss@acb3000 { > + compatible =3D "qcom,sc7280-camss"; > + > + reg =3D <0x0 0x0acb3000 0x0 0x1000>, > + <0x0 0x0acba000 0x0 0x1000>, > + <0x0 0x0acc1000 0x0 0x1000>, > + <0x0 0x0acc8000 0x0 0x1000>, > + <0x0 0x0accf000 0x0 0x1000>, > + <0x0 0x0ace0000 0x0 0x2000>, > + <0x0 0x0ace2000 0x0 0x2000>, > + <0x0 0x0ace4000 0x0 0x2000>, > + <0x0 0x0ace6000 0x0 0x2000>, > + <0x0 0x0ace8000 0x0 0x2000>, > + <0x0 0x0acaf000 0x0 0x4000>, > + <0x0 0x0acb6000 0x0 0x4000>, > + <0x0 0x0acbd000 0x0 0x4000>, > + <0x0 0x0acc4000 0x0 0x4000>, > + <0x0 0x0accb000 0x0 0x4000>; > + reg-names =3D "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY3_CLK>, > + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY4_CLK>, > + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&gcc GCC_CAMERA_AHB_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&camcc CAM_CC_ICP_AHB_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_AXI_CLK>, > + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_0_CSID_CLK>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_1_AXI_CLK>, > + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_1_CSID_CLK>, > + <&camcc CAM_CC_IFE_2_CLK>, > + <&camcc CAM_CC_IFE_2_AXI_CLK>, > + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_2_CSID_CLK>, > + <&camcc CAM_CC_IFE_LITE_0_CLK>, > + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, > + <&camcc CAM_CC_IFE_LITE_1_CLK>, > + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>; > + clock-names =3D "camnoc_axi", > + "cpas_ahb", > + "csiphy0", > + "csiphy0_timer", > + "csiphy1", > + "csiphy1_timer", > + "csiphy2", > + "csiphy2_timer", > + "csiphy3", > + "csiphy3_timer", > + "csiphy4", > + "csiphy4_timer", > + "gcc_camera_ahb", > + "gcc_cam_hf_axi", > + "icp_ahb", > + "vfe0", > + "vfe0_axi", > + "vfe0_cphy_rx", > + "vfe0_csid", > + "vfe1", > + "vfe1_axi", > + "vfe1_cphy_rx", > + "vfe1_csid", > + "vfe2", > + "vfe2_axi", > + "vfe2_cphy_rx", > + "vfe2_csid", > + "vfe_lite0", > + "vfe_lite0_cphy_rx", > + "vfe_lite0_csid", > + "vfe_lite1", > + "vfe_lite1_cphy_rx", > + "vfe_lite1_csid"; > + > + interrupts =3D , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names =3D "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + interconnects =3D <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_= CFG 0>, > + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names =3D "ahb", "hf_0"; > + > + iommus =3D <&apps_smmu 0x800 0x4e0>; > + > + power-domains =3D <&camcc CAM_CC_IFE_0_GDSC>, > + <&camcc CAM_CC_IFE_1_GDSC>, > + <&camcc CAM_CC_IFE_2_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + power-domain-names =3D "ife0", "ife1", "ife2", "top"; > + > + status =3D "disabled"; > + > + ports { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + port@0 { > + reg =3D <0>; > + }; > + > + port@1 { > + reg =3D <1>; > + }; > + > + port@2 { > + reg =3D <2>; > + }; > + > + port@3 { > + reg =3D <3>; > + }; > + > + port@4 { > + reg =3D <4>; > + }; > + }; > + }; > + > camcc: clock-controller@ad00000 { > compatible =3D "qcom,sc7280-camcc"; > reg =3D <0 0x0ad00000 0 0x10000>;