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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-65bad19bfd3sm682707a12.2.2026.02.13.05.39.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Feb 2026 05:39:49 -0800 (PST) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 13 Feb 2026 14:39:48 +0100 Message-Id: From: "Luca Weiss" To: "Konrad Dybcio" , "Luca Weiss" , "Bartosz Golaszewski" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Loic Poulain" , "Robert Foss" , "Andi Shyti" , "Bjorn Andersson" , "Konrad Dybcio" Cc: <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH 4/4] arm64: dts: qcom: milos-fairphone-fp6: Add camera EEPROMs on CCI busses X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260116-milos-cci-v1-0-28e01128da9c@fairphone.com> <20260116-milos-cci-v1-4-28e01128da9c@fairphone.com> <44f65bb6-616c-4dd9-a7a1-ee62d5d217cb@oss.qualcomm.com> In-Reply-To: <44f65bb6-616c-4dd9-a7a1-ee62d5d217cb@oss.qualcomm.com> On Mon Jan 19, 2026 at 11:42 AM CET, Konrad Dybcio wrote: > On 1/16/26 3:54 PM, Luca Weiss wrote: >> On Fri Jan 16, 2026 at 2:59 PM CET, Konrad Dybcio wrote: >>> On 1/16/26 2:38 PM, Luca Weiss wrote: >>>> Enable the CCI I2C busses and add nodes for the EEPROMs found on the >>>> camera that are connected there. >>>> >>>> Signed-off-by: Luca Weiss >>>> --- >>>> arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 50 +++++++++++++++= +++++++++ >>>> 1 file changed, 50 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/a= rm64/boot/dts/qcom/milos-fairphone-fp6.dts >>>> index 7629ceddde2a..c4a706e945ba 100644 >>>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts >>>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts >>>> @@ -529,6 +529,56 @@ vreg_l11f: ldo11 { >>>> }; >>>> }; >>>> =20 >>>> +&cci0 { >>>> + status =3D "okay"; >>>> +}; >>>> + >>>> +&cci0_i2c0 { >>>> + /* Main cam: Sony IMX896 @ 0x1a */ >>>> + >>>> + eeprom@50 { >>>> + compatible =3D "puya,p24c128f", "atmel,24c128"; >>>> + reg =3D <0x50>; >>>> + vcc-supply =3D <&vreg_l6p>; >>>> + read-only; >>>> + }; >>>> + >>>> + /* Dongwoon DW9784 VCM/OIS @ 0x72 */ >>>> +}; >>>> + >>>> + >>>> +&cci0_i2c1 { >>>> + /* Awinic AW86017 VCM @ 0x0c */ >>>> + /* UW cam: OmniVision OV13B10 @ 0x36 */ >>> >>> There's a driver for this one! >>=20 >> Yep! Already got patches to add the required regulators & devicetree >> support to the driver, but since I've got zero on CAMSS so far, I >> couldn't test it more than reading chip ID. > > That means the digital part works.. I'd say it's a good enough > indicator > >>>> + >>>> + eeprom@52 { >>>> + compatible =3D "puya,p24c128f", "atmel,24c128"; >>>> + reg =3D <0x52>; >>>> + vcc-supply =3D <&vreg_l6p>; >>>> + read-only; >>>> + }; >>>> +}; >>>> + >>>> +&cci1 { >>>> + /* cci1_i2c0 is not used for CCI */ >>>> + pinctrl-0 =3D <&cci1_1_default>; >>>> + pinctrl-1 =3D <&cci1_1_sleep>; >>> >>> Let's keep them per-bus-subnode so we don't have to override it >>=20 >> I don't see any upstream example of that, would the pinctrl work >> correctly with that? > > Hmm.. I assumed it would.. and I assumed we do have examples but > ma-a-aybe they got stuck somewhere in the review purgatory? > > If you'd be inclined to test that, you can add a pr_err() to e.g. > msm_pinmux_set_mux() and observe whether that changes as you > interact with the sensor over i2c Yeah that doesn't work. With the following diff I just get some CCI timeouts and at24 driver doesn't probe correctly. I'd prefer not to do some yak shaving to get this patch upstream. Regards Luca diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/= boot/dts/qcom/milos-fairphone-fp6.dts index b6cd95fc294e..9f9410615aea 100644 --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -671,10 +671,6 @@ eeprom@52 { }; =20 &cci1 { - /* cci1_i2c0 is not used for CCI */ - pinctrl-0 =3D <&cci1_1_default>; - pinctrl-1 =3D <&cci1_1_sleep>; - status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index adf050600a4e..a2438cf60271 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1755,9 +1755,6 @@ cci0: cci@ac15000 { clock-names =3D "soc_ahb", "cpas_ahb", "cci"; - pinctrl-0 =3D <&cci0_0_default &cci0_1_default>; - pinctrl-1 =3D <&cci0_0_sleep &cci0_1_sleep>; - pinctrl-names =3D "default", "sleep"; status =3D "disabled"; #address-cells =3D <1>; #size-cells =3D <0>; @@ -1765,6 +1762,9 @@ cci0: cci@ac15000 { cci0_i2c0: i2c-bus@0 { reg =3D <0>; clock-frequency =3D <1000000>; + pinctrl-0 =3D <&cci0_0_default>; + pinctrl-1 =3D <&cci0_0_sleep>; + pinctrl-names =3D "default", "sleep"; #address-cells =3D <1>; #size-cells =3D <0>; }; @@ -1772,6 +1772,9 @@ cci0_i2c0: i2c-bus@0 { cci0_i2c1: i2c-bus@1 { reg =3D <1>; clock-frequency =3D <1000000>; + pinctrl-0 =3D <&cci0_1_default>; + pinctrl-1 =3D <&cci0_1_sleep>; + pinctrl-names =3D "default", "sleep"; #address-cells =3D <1>; #size-cells =3D <0>; }; @@ -1788,9 +1791,6 @@ cci1: cci@ac16000 { clock-names =3D "soc_ahb", "cpas_ahb", "cci"; - pinctrl-0 =3D <&cci1_0_default &cci1_1_default>; - pinctrl-1 =3D <&cci1_0_sleep &cci1_1_sleep>; - pinctrl-names =3D "default", "sleep"; status =3D "disabled"; #address-cells =3D <1>; #size-cells =3D <0>; @@ -1798,6 +1798,9 @@ cci1: cci@ac16000 { cci1_i2c0: i2c-bus@0 { reg =3D <0>; clock-frequency =3D <1000000>; + pinctrl-0 =3D <&cci1_0_default>; + pinctrl-1 =3D <&cci1_0_sleep>; + pinctrl-names =3D "default", "sleep"; #address-cells =3D <1>; #size-cells =3D <0>; }; @@ -1805,6 +1808,9 @@ cci1_i2c0: i2c-bus@0 { cci1_i2c1: i2c-bus@1 { reg =3D <1>; clock-frequency =3D <1000000>; + pinctrl-0 =3D <&cci1_1_default>; + pinctrl-1 =3D <&cci1_1_sleep>; + pinctrl-names =3D "default", "sleep"; #address-cells =3D <1>; #size-cells =3D <0>; };