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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b976d0b5886sm504167566b.65.2026.03.16.01.03.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Mar 2026 01:03:02 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 16 Mar 2026 09:03:01 +0100 Message-Id: Cc: "Konrad Dybcio" , "Krzysztof Kozlowski" , "Bartosz Golaszewski" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Loic Poulain" , "Robert Foss" , "Andi Shyti" , "Bjorn Andersson" , "Konrad Dybcio" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH 2/4] dt-bindings: i2c: qcom-cci: Document Milos compatible From: "Luca Weiss" To: "Dmitry Baryshkov" , "Luca Weiss" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260116-milos-cci-v1-0-28e01128da9c@fairphone.com> <20260116-milos-cci-v1-2-28e01128da9c@fairphone.com> <20260117-obedient-galago-from-eldorado-8e0ba4@quoll> In-Reply-To: On Fri Mar 13, 2026 at 5:18 PM CET, Dmitry Baryshkov wrote: > On Fri, Mar 13, 2026 at 11:43:07AM +0100, Luca Weiss wrote: >> On Fri Feb 13, 2026 at 2:16 PM CET, Luca Weiss wrote: >> > Hi all, >> > >> > On Tue Jan 20, 2026 at 2:18 PM CET, Konrad Dybcio wrote: >> >> On 1/17/26 12:54 PM, Krzysztof Kozlowski wrote: >> >>> On Fri, Jan 16, 2026 at 02:38:56PM +0100, Luca Weiss wrote: >> >>>> Add Milos compatible for the CAMSS CCI interfaces. >> >>>> >> >>>> Signed-off-by: Luca Weiss >> >>>> --- >> >>>> .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 18 ++++++= ++++++++++++ >> >>>> 1 file changed, 18 insertions(+) >> >>>> >> >>>> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yam= l b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml >> >>>> index a3fe1eea6aec..c57d81258fba 100644 >> >>>> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml >> >>>> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml >> >>>> @@ -27,6 +27,7 @@ properties: >> >>>> - items: >> >>>> - enum: >> >>>> - qcom,kaanapali-cci >> >>>> + - qcom,milos-cci >> >>>> - qcom,qcm2290-cci >> >>>> - qcom,sa8775p-cci >> >>>> - qcom,sc7280-cci >> >>>> @@ -263,6 +264,23 @@ allOf: >> >>>> - const: cpas_ahb >> >>>> - const: cci >> >>>> =20 >> >>>> + - if: >> >>>> + properties: >> >>>> + compatible: >> >>>> + contains: >> >>>> + enum: >> >>>> + - qcom,milos-cci >> >>>> + then: >> >>>> + properties: >> >>>> + clocks: >> >>>> + minItems: 3 >> >>>> + maxItems: 3 >> >>>> + clock-names: >> >>>> + items: >> >>>> + - const: soc_ahb >> >>>> + - const: cpas_ahb >> >>>> + - const: cci >> >>>=20 >> >>> Same comments as other discussion these days - I guess that soc_ahb >> >>> serves the same purpose as camnoc_axi, so this is just last entri in= the >> >>> if:then: blocks. >> >>>=20 >> >>> I really find this binding terrible - around six names for AHB - so = I do >> >>> not want another combination... >> >> >> >> I dug up the CCI doc, it talks about the CCI having a CC_CCI_CLK cloc= k ("cci" >> >> here) and a CC_PBUS_CLK (AHB interface to the rest of the SoC). >> >> >> >> The CAMSS TOP doc (for Milos specifically, but I would assume there's= a >> >> pattern) says that for access to CCI_0, I need to enable CAM_CC_CPAS_= AHB_CLK >> >> and CAM_CC_CCI_0_CLK. CPAS is a wrapper inside CAMSS that contains mo= st of >> >> the programmable IPs on there (notably not the CSIPHYs, at least not = on this >> >> platform) >> >> >> >> It further mentions that GCC_SOC_AHB_CLK is required for *any* regist= er >> >> access within CAMSS. Perhaps it sits right in front of the xNoC-to-CA= MNoC >> >> interface. >> >> >> >> This only enforces my imagination of CAMSS being a fully contained "b= us" >> >> (perhaps somewhat like AxNOC on 8996 represented with a simple-pm-bus= ).. >> >> >> >> +Dmitry, myself and a number of our colleagues were deliberating how = to >> >> best represent the hardware going forward and I think we at some poin= t waved >> >> the idea of putting every camera subdevice under a "camss: bus@ {}"-t= ype node, >> >> which would hold the reference to the TITAN_TOP_GDSC. This seems fitt= ing for >> >> housing the SOC_AHB clock as well and therefore concluding this discu= ssion. >> > >> > How can we continue here? What change can I do to unblock this? I can'= t >> > tell whether soc_ahb =3D=3D camnoc_axi for this platform so I need som= e help >> > here. >>=20 >> Any feedback on this? > > I went on and checked. No Milos's soc_ahb !=3D camnoc_axi. They serve > different purposes. Thanks Dmitry, appreciate it! @Krzysztof: Could you take another look at the binding then please? Regards Luca