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[2001:1c00:3b89:c600:71a4:84f:6409:1447]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-67cd904fe68sm297388a12.0.2026.05.05.03.49.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 May 2026 03:49:58 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 05 May 2026 12:49:57 +0200 Message-Id: Cc: "Bjorn Andersson" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Konrad Dybcio" , "Srinivas Kandagatla" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , , "Konrad Dybcio" , "Dmitry Baryshkov" Subject: Re: [PATCH v2 0/5] Add LPASS LPI pin controller support for SM6350 From: "Luca Weiss" To: "Linus Walleij" , "Luca Weiss" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260430-sm6350-lpi-tlmm-v2-0-81d068025b97@fairphone.com> In-Reply-To: On Tue May 5, 2026 at 12:35 PM CEST, Linus Walleij wrote: > On Thu, Apr 30, 2026 at 9:10=E2=80=AFAM Luca Weiss wrote: > >> Introduce support for the LPASS LPI pin controller for the Qualcomm >> SM6350 SoC, by adding the dt-bindings, driver, dts bits and enabling it >> in the arm64 defconfig. >> >> The custom slew offset for gpio14 is described as >> "qcom,lpi-slew-base-tbl" in the downstream dts[0]. I've tried to find >> some reasonable solution to have this handled correctly in the patches >> here, but suggestions are welcome how to improve the situation. There's >> of course several ways to implement a solution for this. >> >> [0] https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-= extra/devicetree/+/refs/heads/kernel/13/fp4/qcom/lagoon-lpi.dtsi#25 >> >> Signed-off-by: Luca Weiss > > Fixed up Kconfig text and applied patches 1, 2 and 3 to the pinctrl tree. > > Please funnel patches 4 & 5 through the SoC tree (Bjorn Andersson, > I think.) Great, thank you!