From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F815C4332F for ; Thu, 10 Nov 2022 10:53:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230235AbiKJKxq (ORCPT ); Thu, 10 Nov 2022 05:53:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230132AbiKJKxp (ORCPT ); Thu, 10 Nov 2022 05:53:45 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B33520F47; Thu, 10 Nov 2022 02:53:45 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DDD546118D; Thu, 10 Nov 2022 10:53:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 371B4C433C1; Thu, 10 Nov 2022 10:53:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668077624; bh=NIkFOvlY2E8XiQDmpV5S1/Wj5B+wkYmLdAyQTN8UlYI=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=OLBkQY41+ePvBdmK4e0Q2MjEFJxdWo4JJMDCuSJoFiLEhOdPNrprENFxufqyr+N3e RZ7PfTJy1PkCDXTIQFV+QMDQHKgZRmW8EwM4vjFKGsPOZqx52vWhaMfmU7zSeVuVEu tHus/nKEKLx5EFgSuFzxqucndhOn9+uv+h4ohX49EMhUjhzPQrq9i9S7H/JzfulRcG 2LuN54h1UvNZam/QqfjxsUqA1dL3to/KoUpbQMc1KJgAweC7adbPQ2LuywA3B3A4Cn jx53s0ighWRcFzi0jhSpR3PcVet2Bj8xHfRlgusQ8n22/HyIv1bA2ilFxB28sYBflY ZimwosnMTGyXA== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ot5BM-0003Yf-S0; Thu, 10 Nov 2022 11:53:16 +0100 Date: Thu, 10 Nov 2022 11:53:16 +0100 From: Johan Hovold To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices Message-ID: References: <20221110103345.729018-1-dmitry.baryshkov@linaro.org> <20221110103345.729018-8-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221110103345.729018-8-dmitry.baryshkov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, Nov 10, 2022 at 01:33:44PM +0300, Dmitry Baryshkov wrote: > Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350 > platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host. > > Signed-off-by: Dmitry Baryshkov > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 246 ++++++++++++++++++++++++++- > 1 file changed, 244 insertions(+), 2 deletions(-) > @@ -1761,6 +1957,52 @@ tlmm: pinctrl@f100000 { > gpio-ranges = <&tlmm 0 0 204>; > wakeup-parent = <&pdc>; > > + pcie0_default_state: pcie0-default-state { > + perst-pins { > + pins = "gpio94"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + clkreq-pins { > + pins = "gpio95"; > + function = "pcie0_clkreqn"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + wake-pins { > + pins = "gpio96"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; The pinconfig should go in the board file. Johan