From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E59F8C4332F for ; Thu, 24 Nov 2022 17:56:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229580AbiKXR4H (ORCPT ); Thu, 24 Nov 2022 12:56:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229719AbiKXRzy (ORCPT ); Thu, 24 Nov 2022 12:55:54 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BD95194; Thu, 24 Nov 2022 09:55:49 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CC264621DE; Thu, 24 Nov 2022 17:55:48 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B724FC433D6; Thu, 24 Nov 2022 17:55:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669312548; bh=xH37rU92E/kj6aTEHXMGsvG6PRFtudz6lokNA2S+mRU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=YyHi3JhrgHrYiaAtm2RTMaq/L1coulhGLBwknLFKi77bLwEuv8n5jH6CeCv15AWEk 0M5DQ/NqT+xl6SyX9dL/b3u7Iitob1CCeGYrFFkfhc4dJH4jRpYB2/tgkbKWE8/Tk9 RYZgL/2CrSdWOXNOn1OPgApdbTfmK9OhQxzVpINWTs1vaaqE4lf3XoNi9K23XvbE8D YYydmesB0cEBkejcsJ0Sjot0Q31Nlx8U0GcAY42WWzl7tIm76+LKVHFOK+0UaGyhGZ KB+h70hHWGBr4moXRCMONQbylcaC+EEbV3eVRlKqy5FW+fY0eWM0MD8bCSHekoNTjY pRZ05eW8iULrA== Date: Thu, 24 Nov 2022 23:25:44 +0530 From: Vinod Koul To: Abel Vesa Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH 03/10] phy: qcom-qmp-ufs: Add SM8550 support Message-ID: References: <20221116120157.2706810-1-abel.vesa@linaro.org> <20221116120157.2706810-4-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221116120157.2706810-4-abel.vesa@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 16-11-22, 14:01, Abel Vesa wrote: > Add SM8550 specific register layout and table configs. > > Signed-off-by: Abel Vesa > --- > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 91 +++++++++++++++++++++++++ > 1 file changed, 91 insertions(+) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > index 189103d1bd18..14cb716752e6 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > @@ -96,6 +96,13 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { > [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, > }; > > +static const unsigned int sm8550_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { > + [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, > + [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, > + [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET, > + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, > +}; > + > static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { > QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), > @@ -520,6 +527,65 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { > QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > }; > > +static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { > + QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), > +}; Unused? > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { > + QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), > + > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), > + > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), > + > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > +}; > + > struct qmp_ufs_offsets { > u16 serdes; > u16 pcs; > @@ -613,6 +679,10 @@ static const char * const sm8450_ufs_phy_clk_l[] = { > "qref", "ref", "ref_aux", > }; > > +static const char * const sm8550_ufs_phy_clk_l[] = { > + "qref", "ref", > +}; > + > static const char * const sdm845_ufs_phy_clk_l[] = { > "ref", "ref_aux", > }; > @@ -766,6 +836,24 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { > .regs = sm8150_ufsphy_regs_layout, > }; > > +static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { > + .lanes = 2, > + > + .serdes_tbl = sm8550_ufsphy_serdes, > + .serdes_tbl_num = ARRAY_SIZE(sm8550_ufsphy_serdes), > + .tx_tbl = sm8550_ufsphy_tx, > + .tx_tbl_num = ARRAY_SIZE(sm8550_ufsphy_tx), > + .rx_tbl = sm8550_ufsphy_rx, > + .rx_tbl_num = ARRAY_SIZE(sm8550_ufsphy_rx), > + .pcs_tbl = sm8550_ufsphy_pcs, > + .pcs_tbl_num = ARRAY_SIZE(sm8550_ufsphy_pcs), > + .clk_list = sm8550_ufs_phy_clk_l, > + .num_clks = ARRAY_SIZE(sm8550_ufs_phy_clk_l), > + .vreg_list = qmp_phy_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), > + .regs = sm8550_ufsphy_regs_layout, > +}; > + > static void qmp_ufs_configure_lane(void __iomem *base, > const struct qmp_phy_init_tbl tbl[], > int num, > @@ -1189,6 +1277,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { > }, { > .compatible = "qcom,sm8450-qmp-ufs-phy", > .data = &sm8450_ufsphy_cfg, > + }, { > + .compatible = "qcom,sm8550-qmp-ufs-phy", > + .data = &sm8550_ufsphy_cfg, > }, > { }, > }; > -- > 2.34.1 -- ~Vinod