From: Johan Hovold <johan@kernel.org>
To: Brian Masney <bmasney@redhat.com>
Cc: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org,
agross@kernel.org, konrad.dybcio@linaro.org, robh+dt@kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, quic_shazhuss@quicinc.com,
psodagud@quicinc.com, ahalaney@redhat.com, echanude@redhat.com
Subject: Re: [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support
Date: Tue, 6 Dec 2022 16:50:46 +0100 [thread overview]
Message-ID: <Y49k1k8ayI9/rK+R@hovoldconsulting.com> (raw)
In-Reply-To: <20221202120918.2252647-1-bmasney@redhat.com>
On Fri, Dec 02, 2022 at 07:09:18AM -0500, Brian Masney wrote:
> Add the vreg_l11a, pcie3a, pcie3a_phy, and tlmm nodes that are necessary
> in order to get PCIe working on the QDrive3.
> @@ -158,6 +186,31 @@ &remoteproc_nsp1 {
> status = "okay";
> };
>
> +&tlmm {
> + pcie3a_default: pcie3a-default-state {
> + perst-pins {
> + pins = "gpio151";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + clkreq-pins {
> + pins = "gpio150";
> + function = "pcie3a_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + wake-pins {
> + pins = "gpio56";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +};
> +
The pin configuration nodes typically go last after a
/* PINCTRL */
delimiter as this section tends to become rather long.
> &ufs_mem_hc {
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
Johan
next prev parent reply other threads:[~2022-12-06 15:51 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-02 12:09 [PATCH v3] arm64: dts: qcom: sa8540p-ride: enable PCIe support Brian Masney
2022-12-02 20:43 ` Andrew Halaney
2022-12-06 13:50 ` Shazad Hussain
2022-12-06 15:50 ` Johan Hovold [this message]
2022-12-06 18:18 ` Bjorn Andersson
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