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Date:   Wed, 18 Jan 2023 22:55:43 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc:     Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Kishon Vijay Abraham I <kishon@kernel.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH 1/2] phy: qcom-qmp-pcie: fix the regs layout table for
 sm8450 gen3x1 PHY
Message-ID: <Y8grl2UjkGTOo/Y5@matsya>
References: <20230113212138.421583-1-dmitry.baryshkov@linaro.org>
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On 13-01-23, 23:21, Dmitry Baryshkov wrote:
> The sm8450 gen3x1 PHY references the pciephy_v4_regs_layout while the
> PHY itself uses v5 regs. While there are only minor differences between
> v4 and v5 regs and none of them concerns registers mentions in
> regs_layout, switch the PHY to use pciephy_v5_regs_layout to remove
> possible confusion.

Applied both, thanks

-- 
~Vinod