From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0DDCCC4332B for ; Wed, 3 Mar 2021 21:52:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CD29564F0B for ; Wed, 3 Mar 2021 21:52:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1389663AbhCCVjx (ORCPT ); Wed, 3 Mar 2021 16:39:53 -0500 Received: from mga01.intel.com ([192.55.52.88]:14620 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1381256AbhCCOUN (ORCPT ); Wed, 3 Mar 2021 09:20:13 -0500 IronPort-SDR: 9/kd3Ev2llRq0e7STPkZMO1+gFE9rSvw2aSysCdWLuKcNmTtM/kgCORFzA8xFl8AS9qZZ3UyCm AkI2rVwwCIPA== X-IronPort-AV: E=McAfee;i="6000,8403,9911"; a="206886538" X-IronPort-AV: E=Sophos;i="5.81,220,1610438400"; d="scan'208";a="206886538" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2021 06:08:37 -0800 IronPort-SDR: rMmN4KZ3fdmDZeDj8gNHlBwzYJ9ZVGaN8fzu6nNl3HjsxWFc+L8Ve36pbOYHuW3wIyTMbAQlyQ wXutivSG/f5A== X-IronPort-AV: E=Sophos;i="5.81,220,1610438400"; d="scan'208";a="445283548" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Mar 2021 06:08:35 -0800 Received: from andy by smile with local (Exim 4.94) (envelope-from ) id 1lHSAy-009eRy-Td; Wed, 03 Mar 2021 16:08:32 +0200 Date: Wed, 3 Mar 2021 16:08:32 +0200 From: Andy Shevchenko To: Shawn Guo Cc: Linus Walleij , Bjorn Andersson , linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v2] pinctrl: qcom: support gpio_chip .set_config call Message-ID: References: <20210303131858.3976-1-shawn.guo@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210303131858.3976-1-shawn.guo@linaro.org> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed, Mar 03, 2021 at 09:18:58PM +0800, Shawn Guo wrote: > In case of ACPI boot, GPIO core does the right thing to parse GPIO pin > configs from ACPI table, and call into gpio_chip's .set_config hook for > setting them up. It enables such support on qcom platform by using > generic config function, which in turn calls into .pin_config_set of > pinconf for setting up hardware. For qcom platform, it's possible to > reuse pin group config functions for pin config hooks, because every pin > is maintained as a single group. > > This change fixes the problem that Touchpad of Lenovo Flex 5G laptop > doesn't work with ACPI boot, because PullUp config of Touchpad GpioInt > pin is not set up by the kernel. FWIW, Reviewed-by: Andy Shevchenko > Signed-off-by: Shawn Guo > --- > Changes for v2: > - Add pin config functions that simply call into group config ones. > > drivers/pinctrl/qcom/pinctrl-msm.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index af6ed7f43058..a59bb4cbd97e 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -489,10 +489,24 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, > return 0; > } > > +static int msm_config_pin_get(struct pinctrl_dev *pctldev, unsigned int pin, > + unsigned long *config) > +{ > + return msm_config_group_get(pctldev, pin, config); > +} > + > +static int msm_config_pin_set(struct pinctrl_dev *pctldev, unsigned pin, > + unsigned long *configs, unsigned num_configs) > +{ > + return msm_config_group_set(pctldev, pin, configs, num_configs); > +} > + > static const struct pinconf_ops msm_pinconf_ops = { > .is_generic = true, > .pin_config_group_get = msm_config_group_get, > .pin_config_group_set = msm_config_group_set, > + .pin_config_get = msm_config_pin_get, > + .pin_config_set = msm_config_pin_set, > }; > > static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) > @@ -717,6 +731,7 @@ static const struct gpio_chip msm_gpio_template = { > .get_direction = msm_gpio_get_direction, > .get = msm_gpio_get, > .set = msm_gpio_set, > + .set_config = gpiochip_generic_config, > .request = gpiochip_generic_request, > .free = gpiochip_generic_free, > .dbg_show = msm_gpio_dbg_show, > -- > 2.17.1 > -- With Best Regards, Andy Shevchenko