From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEE2BC43460 for ; Thu, 22 Apr 2021 18:35:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B354661425 for ; Thu, 22 Apr 2021 18:35:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238434AbhDVSfe (ORCPT ); Thu, 22 Apr 2021 14:35:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236973AbhDVSfd (ORCPT ); Thu, 22 Apr 2021 14:35:33 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 977FEC06138C for ; Thu, 22 Apr 2021 11:34:57 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id h15so14648149pfv.2 for ; Thu, 22 Apr 2021 11:34:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=fIQGP5hbKxQ2AbrjuHVsEc+gLwD1Ifi6sPdpnHLAXEU=; b=f8UNiwNy63Nq+gwYfc7TIo47CogfxT77XpfYfYqcuRTxf5Ttw5fmjTdRT/R+GjVmtn bEm3Y+0dxjATq63vvrh2z8+1lfcFFPc8Xv6M5vssBo47Kb8VlXxRMgAFGuD2NTGowJ0f Y/W8f495wGtkVKqTfrPo52qW4vMgG0ZcCdcKQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=fIQGP5hbKxQ2AbrjuHVsEc+gLwD1Ifi6sPdpnHLAXEU=; b=Fhem6NrpMT4v9uDCvgYgt1293u7PeuNMN6PKwbPgJMH8qdAavkSVpLh3e9tYbymw26 VOUb4Ufzerpk0J2iYmoJNSXpVcBftuOLYVzIzPy5A+z61T4JT5Iz0NjSjxAJgVBzSXCX KtjJ4gDr6WruKaGEOlOCfHkP4E7IL6mZB/UbczzpTV4A3QXeeXRY4iJQ5V4rf8Ct1BFO 7JuoImG2ipD9Xmap0Lq/sgGZd3HcMjuCzTZ1vEJHCTNENkFqmCJSQlUEO+jxO/IgDU0e QZ8836v0X5B4SnhJcK/TlIARkixb8xgaQdTYntb9QoG4A/mKuBBoFFv8C+ueV0eZ0Hpt WDTg== X-Gm-Message-State: AOAM533jWtZkiBfyuTYZKFqg/kvU3+/+mTVHBNh3yVikVu8HN2axjesd H8rKYiTd+sygQP5D2dDCsba5Rg== X-Google-Smtp-Source: ABdhPJxQXisVXNdHeC/K1YPSaxq3pq+fVgXtyyRPEWHARZ9IremNzgNVlEy4hhINfix50PAx5/0CRA== X-Received: by 2002:aa7:87d3:0:b029:259:ff63:3500 with SMTP id i19-20020aa787d30000b0290259ff633500mr85995pfo.35.1619116497024; Thu, 22 Apr 2021 11:34:57 -0700 (PDT) Received: from localhost ([2620:15c:202:201:acff:4f9f:d039:23ff]) by smtp.gmail.com with UTF8SMTPSA id t19sm2884558pfg.38.2021.04.22.11.34.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Apr 2021 11:34:56 -0700 (PDT) Date: Thu, 22 Apr 2021 11:34:55 -0700 From: Matthias Kaehlcke To: Sandeep Maheswaram Cc: Rob Herring , Andy Gross , Bjorn Andersson , Greg Kroah-Hartman , Felipe Balbi , Stephen Boyd , Doug Anderson , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Manu Gautam Subject: Re: [PATCH v2] arm64: dts: qcom: sc7280: Add USB related nodes Message-ID: References: <1619112931-2144-1-git-send-email-sanm@codeaurora.org> <1619112931-2144-2-git-send-email-sanm@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1619112931-2144-2-git-send-email-sanm@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, Apr 22, 2021 at 11:05:31PM +0530, Sandeep Maheswaram wrote: > Add nodes for DWC3 USB controller, QMP and HS USB PHYs. > > Signed-off-by: Sandeep Maheswaram > --- What changes with respect to v1? Please always include a change log for versions > 1 > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 40 +++++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 150 ++++++++++++++++++++++++++++++++ > 2 files changed, 190 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > index 54d2cb3..f1998d8 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts I suggest to split this into two patches, one for the SoC and one for the board (IDP). That way it is evident from the subject what each patch does and reverts could be done individually if needed. > @@ -242,6 +242,46 @@ > status = "okay"; > }; > > + don't add a second empty line > +&usb_1 { > + status = "okay"; > +}; > + > +&usb_1_dwc3 { > + dr_mode = "host"; > +}; > + > +&usb_1_hsphy { > + status = "okay"; > + > + vdda-pll-supply = <&vreg_l10c_0p8>; > + vdda33-supply = <&vreg_l2b_3p0>; > + vdda18-supply = <&vreg_l1c_1p8>; > +}; > + > +&usb_1_qmpphy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l6b_1p2>; > + vdda-pll-supply = <&vreg_l1b_0p8>; > +}; > + > +&usb_2 { > + status = "okay"; > +}; > + > +&usb_2_dwc3 { > + dr_mode = "peripheral"; > +}; > + > +&usb_2_hsphy { > + status = "okay"; > + > + vdda-pll-supply = <&vreg_l10c_0p8>; > + vdda33-supply = <&vreg_l2b_3p0>; > + vdda18-supply = <&vreg_l1c_1p8>; > +}; > + > /* PINCTRL - additions to nodes defined in sc7280.dtsi */ > > &qup_uart5_default { > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 2cc4785..8323f53 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -805,6 +805,110 @@ > }; > }; > > + usb_1_hsphy: phy@88e3000 { > + compatible = "qcom,sc7280-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e3000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + }; > + > + usb_2_hsphy: phy@88e4000 { > + compatible = "qcom,sc7280-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e4000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; > + }; > + > + usb_1_qmpphy: phy-wrapper@88e9000 { > + compatible = "qcom,sm8250-qmp-usb3-phy"; > + reg = <0 0x088e9000 0 0x200>, > + <0 0x088e8000 0 0x20>; > + reg-names = "reg-base", "dp_com"; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > + clock-names = "aux", "ref_clk_src", "com_aux"; > + > + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_PHY_PRIM_BCR>; > + reset-names = "phy", "common"; > + > + usb_1_ssphy: usb3-phy@88e9200 { > + reg = <0 0x088e9200 0 0x200>, > + <0 0x088e9400 0 0x200>, > + <0 0x088e9c00 0 0x400>, > + <0 0x088e9600 0 0x200>, > + <0 0x088e9800 0 0x200>, > + <0 0x088e9a00 0 0x100>; > + #phy-cells = <0>; > + #clock-cells = <1>; > + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "usb3_phy_pipe_clk_src"; > + }; > + }; > + > + usb_2: usb@8cf8800 { > + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; > + reg = <0 0x08cf8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, > + <&gcc GCC_USB30_SEC_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, > + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SEC_SLEEP_CLK>; > + clock-names = "cfg_noc", "core", "iface","mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SEC_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 13 IRQ_TYPE_EDGE_RISING>, > + <&pdc 12 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "hs_phy_irq", > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > + > + power-domains = <&gcc GCC_USB30_SEC_GDSC>; > + > + resets = <&gcc GCC_USB30_SEC_BCR>; > + > + usb_2_dwc3: dwc3@8c00000 { > + compatible = "snps,dwc3"; > + reg = <0 0x08c00000 0 0xe000>; > + interrupts = ; > + iommus = <&apps_smmu 0xa0 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_2_hsphy>; > + phy-names = "usb2-phy"; > + maximum-speed = "high-speed"; > + }; > + }; > + > system-cache-controller@9200000 { > compatible = "qcom,sc7280-llcc"; > reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; > @@ -812,6 +916,52 @@ > interrupts = ; > }; > > + usb_1: usb@a6f8800 { > + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; > + nit: remove empty line (as for 'usb_2' above), 'clocks' and 'clock-names' belong together > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", > + "dm_hs_phy_irq", "ss_phy_irq"; > + > + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + > + usb_1_dwc3: dwc3@a600000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a600000 0 0xe000>; > + interrupts = ; > + iommus = <&apps_smmu 0xe0 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + maximum-speed = "super-speed"; > + }; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sc7280-pdc", "qcom,pdc"; > reg = <0 0x0b220000 0 0x30000>;