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[66.90.148.213]) by smtp.gmail.com with ESMTPSA id 4sm3768624ooa.11.2021.08.31.12.02.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Aug 2021 12:02:29 -0700 (PDT) Received: (nullmailer pid 479023 invoked by uid 1000); Tue, 31 Aug 2021 19:02:28 -0000 Date: Tue, 31 Aug 2021 14:02:28 -0500 From: Rob Herring To: Baruch Siach Cc: Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Lee Jones , Andy Gross , Bjorn Andersson , Balaji Prakash J , Robert Marko , Kathiravan T , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v8 3/4] dt-bindings: pwm: add IPQ6018 binding Message-ID: References: <5c95bcf62a9d08208a7da19f0b1cec0689502b9a.1630323987.git.baruch@tkos.co.il> <8238dfb5d5e4a40a995f047db36d9a7240431de5.1630323987.git.baruch@tkos.co.il> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <8238dfb5d5e4a40a995f047db36d9a7240431de5.1630323987.git.baruch@tkos.co.il> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Mon, Aug 30, 2021 at 02:46:26PM +0300, Baruch Siach wrote: > DT binding for the PWM block in Qualcomm IPQ6018 SoC. > > Signed-off-by: Baruch Siach > --- > This series does not convert the TCSR binding documentation to YAML. As > a result, this commit adds new a dt_binding_check warning: > > /example-0/syscon@1937000: failed to match any schema with compatible: ['qcom,tcsr-ipq 6018', 'syscon', 'simple-mfd'] > > If that is a blocker to IPQ6018 PWM support, so be it. Patches will wait > for someone else to push them further. > > v8: > > Add size cell to 'reg' (Rob) > > v7: > > Use 'reg' instead of 'offset' (Rob) > > Drop 'clock-names' and 'assigned-clock*' (Bjorn) > > Use single cell address/size in example node (Bjorn) > > Move '#pwm-cells' lower in example node (Bjorn) > > List 'reg' as required > > v6: > > Device node is child of TCSR; remove phandle (Rob Herring) > > Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König) > > v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn > Andersson, Kathiravan T) > > v4: Update the binding example node as well (Rob Herring's bot) > > v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) > > v2: Make #pwm-cells const (Rob Herring) > --- > .../devicetree/bindings/pwm/ipq-pwm.yaml | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > new file mode 100644 > index 000000000000..96bc63e336bf > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > @@ -0,0 +1,52 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm IPQ6018 PWM controller > + > +maintainers: > + - Baruch Siach > + > +properties: > + "#pwm-cells": > + const: 2 > + > + compatible: > + const: qcom,ipq6018-pwm > + > + reg: > + description: Offset of PWM register in the TCSR block. > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - "#pwm-cells" > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + tcsr: syscon@1937000 { Drop unused (by the example) labels. > + compatible = "qcom,tcsr-ipq6018", "syscon", "simple-mfd"; > + reg = <0x01937000 0x21000>; > + #address-cells = <1>; > + #size-cells = <1>; ranges = <0 0x1937000 0x21000>; Otherwise, the address is not translatable. > + > + pwm: pwm@a010 { > + compatible = "qcom,ipq6018-pwm"; > + reg = <0xa010 0x20>; > + clocks = <&gcc GCC_ADSS_PWM_CLK>; > + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; > + assigned-clock-rates = <100000000>; > + #pwm-cells = <2>; > + }; > + }; > -- > 2.33.0 > >