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charset=utf-8 Content-Disposition: inline In-Reply-To: <1629983731-10595-4-git-send-email-rajpat@codeaurora.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Thu, Aug 26, 2021 at 06:45:27PM +0530, Rajesh Patil wrote: > From: Roja Rani Yarubandi > > Add QUPv3 wrapper_0 DT nodes for SC7280 SoC. > > Signed-off-by: Roja Rani Yarubandi > Signed-off-by: Rajesh Patil > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 724 ++++++++++++++++++++++++++++++++++- > 1 file changed, 722 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index f8dd5ff..da3cf19 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -434,6 +434,25 @@ > }; > }; > > + qup_opp_table: qup-opp-table { > + compatible = "operating-points-v2"; > + > + opp-75000000 { > + opp-hz = /bits/ 64 <75000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-128000000 { > + opp-hz = /bits/ 64 <128000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + > soc: soc@0 { > #address-cells = <2>; > #size-cells = <2>; > @@ -536,24 +555,425 @@ > qupv3_id_0: geniqup@9c0000 { > compatible = "qcom,geni-se-qup"; > reg = <0 0x009c0000 0 0x2000>; > - clock-names = "m-ahb", "s-ahb"; > clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + clock-names = "m-ahb", "s-ahb"; > #address-cells = <2>; > #size-cells = <2>; > ranges; > + iommus = <&apps_smmu 0x123 0x0>; > status = "disabled"; > > + i2c0: i2c@980000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00980000 0 0x4000>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + clock-names = "se"; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c0_data_clk>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, > + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "qup-core", "qup-config", > + "qup-memory"; > + status = "disabled"; > + }; > + > + spi0: spi@980000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00980000 0 0x4000>; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + clock-names = "se"; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>, <&qup_spi0_cs_gpio>; as per the discussion on v5 (https://patchwork.kernel.org/project/linux-arm-msm/patch/1628754078-29779-4-git-send-email-rajpat@codeaurora.org/) I remain unconvinced that configuring the CS pin both as CS and GPIO is a good idea. If you think it is necessary in this case (maybe some kind of quirk?) please provide a rationale.