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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id c10-20020a4ad78a000000b004256a36a217sm6322108oou.34.2022.06.27.13.02.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 13:02:19 -0700 (PDT) Date: Mon, 27 Jun 2022 15:02:17 -0500 From: Bjorn Andersson To: Bjorn Helgaas Cc: Dmitry Baryshkov , Andy Gross , Stephen Boyd , Michael Turquette , Taniya Das , Lorenzo Pieralisi , Krzysztof Wilczy??ski , Bjorn Helgaas , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org, Johan Hovold , kernel test robot Subject: Re: [PATCH v11 1/5] clk: qcom: regmap: add PHY clock source implementation Message-ID: References: <20220608105238.2973600-2-dmitry.baryshkov@linaro.org> <20220608192233.GA413725@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220608192233.GA413725@bhelgaas> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed 08 Jun 14:22 CDT 2022, Bjorn Helgaas wrote: > On Wed, Jun 08, 2022 at 01:52:34PM +0300, Dmitry Baryshkov wrote: > > On recent Qualcomm platforms the QMP PIPE clocks feed into a set of > > muxes which must be parked to the "safe" source (bi_tcxo) when > > corresponding GDSC is turned off and on again. Currently this is > > handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src > > clock. However the same code sequence should be applied in the > > pcie-qcom endpoint, USB3 and UFS drivers. > > > > Rather than copying this sequence over and over again, follow the > > example of clk_rcg2_shared_ops and implement this parking in the > > enable() and disable() clock operations. Supplement the regmap-mux with > > the new clk_regmap_phy_mux type, which implements such multiplexers > > as a simple gate clocks. > > > > This is possible since each of these multiplexers has just two clock > > sources: one coming from the PHY and a reference (XO) one. If the clock > > is running off the from-PHY source, report it as enabled. Report it as > > disabled otherwise (if it uses reference source). > > > > This way the PHY will disable the pipe clock before turning off the > > GDSC, which in turn would lead to disabling corresponding pipe_clk_src > > (and thus it being parked to a safe, reference clock source). And vice > > versa, after enabling the GDSC the PHY will enable the pipe clock, which > > would cause pipe_clk_src to be switched from a safe source to the > > working one. > > > > Reviewed-by: Johan Hovold > > Tested-by: Johan Hovold > > Reported-by: kernel test robot > > Signed-off-by: Dmitry Baryshkov > > --- > > drivers/clk/qcom/Makefile | 1 + > > drivers/clk/qcom/clk-regmap-phy-mux.c | 62 +++++++++++++++++++++++++++ > > drivers/clk/qcom/clk-regmap-phy-mux.h | 33 ++++++++++++++ > > 3 files changed, 96 insertions(+) > > create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.c > > create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.h > > Since it's posted as part of the series, I assume this should all be > applied together, so I'll look for an ack from Bjorn Andersson > , maintainer of drivers/clk/qcom. Hi Bjorn, Picking the clock patch through the clock tree would allow us to fix up additional platforms (analog to patch 2 & 3) in time for v5.20 and reduces risk for merge conflicts. So please find an immutable branch (tag) of the clock patches here: https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git tags/20220608105238.2973600-1-dmitry.baryshkov@linaro.org Hope this suits you. Regards, Bjorn