From: Vinod Koul <vkoul@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@somainline.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Kishon Vijay Abraham I" <kishon@ti.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Johan Hovold" <johan@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org
Subject: Re: [PATCH v3 1/9] phy: define submodes for PCIe PHYs
Date: Sat, 24 Sep 2022 11:48:15 +0530 [thread overview]
Message-ID: <Yy6hJyivbbQ+sI3n@matsya> (raw)
In-Reply-To: <20220909091433.3715981-2-dmitry.baryshkov@linaro.org>
On 09-09-22, 12:14, Dmitry Baryshkov wrote:
> Define two submodes to be used for the PCIe PHYs, where required.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> include/linux/phy/phy.h | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
> index b1413757fcc3..bd60c1a72988 100644
> --- a/include/linux/phy/phy.h
> +++ b/include/linux/phy/phy.h
> @@ -45,6 +45,15 @@ enum phy_mode {
> PHY_MODE_DP
> };
>
> +/*
> + * Submodes for the PHY_MODE_PCIE, allowing the host to select between RC (Root
> + * Complex) and EP (End Point) PHY modes.
> + */
> +enum {
> + PHY_SUBMODE_PCIE_RC,
> + PHY_SUBMODE_PCIE_EP,
> +};
This can be dropped see include/linux/phy/pcie.h
> +
> enum phy_media {
> PHY_MEDIA_DEFAULT,
> PHY_MEDIA_SR,
> --
> 2.35.1
--
~Vinod
next prev parent reply other threads:[~2022-09-24 6:18 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-09 9:14 [PATCH v3 0/9] PCI: qcom: Support using the same PHY for both RC and EP Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 1/9] phy: define submodes for PCIe PHYs Dmitry Baryshkov
2022-09-24 6:18 ` Vinod Koul [this message]
2022-09-09 9:14 ` [PATCH v3 2/9] phy: qcom-qmp-pcie: drop if (table) conditions Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 3/9] phy: qcom-qmp-pcie: split register tables into main and secondary parts Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 4/9] phy: qcom-qmp-pcie: split PHY programming to separate functions Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 5/9] phy: qcom-qmp-pcie: turn secondary programming table into a pointer Dmitry Baryshkov
2022-09-14 6:59 ` Johan Hovold
2022-09-09 9:14 ` [PATCH v3 6/9] phy: qcom-qmp-pcie: support separate tables for EP mode Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 7/9] phy: qcom-qmp-pcie: Support SM8450 PCIe1 PHY in " Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 8/9] PCI: qcom: Setup PHY to work in RC mode Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 9/9] PCI: qcom-ep: Setup PHY to work in EP mode Dmitry Baryshkov
2022-09-14 6:48 ` [PATCH v3 0/9] PCI: qcom: Support using the same PHY for both RC and EP Johan Hovold
2022-09-24 5:48 ` Vinod Koul
2022-09-26 7:09 ` Johan Hovold
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