From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6642C07E9D for ; Mon, 26 Sep 2022 06:32:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232569AbiIZGcm (ORCPT ); Mon, 26 Sep 2022 02:32:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231396AbiIZGcl (ORCPT ); Mon, 26 Sep 2022 02:32:41 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E50A2A94A; Sun, 25 Sep 2022 23:32:40 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 123506174E; Mon, 26 Sep 2022 06:32:40 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5FDF8C433D6; Mon, 26 Sep 2022 06:32:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664173959; bh=lT31F5ekIodvNrPjS3UIG91uixWX4XDbQLqZYYRxJ/c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=GpSpRIjyWDkExpn9J8XqEW87+YelDlRYpN3D1ElL4PTr7zwhnUprfSqDLD56FAlqH XjQfjaVoBeefh7HmeFQoZesv4IiNlEBewYi4hsp3teZy9u+EF1D98fvX3lGSPnljI1 UTLfnsdiGor8zMJ8314shzPG1wTVSbWVR7SNyno/Pkbjw430hUgFvJhNv/q/7BDF/R Tc94klDxp9aZB1bETNITb8KqXtEaFTgry4gpPaT87tpJhaJIfu43sYWXevHviZtAcA m8vTCCV20gXzBoeUDg9gF+2etH/Lk0OtKwR0VZ5giw3gBOg9aPI2wvRgndgf+hhg3L 242XEmfN6XOug== Received: from johan by xi.lan with local (Exim 4.94.2) (envelope-from ) id 1ochfX-00028l-Qm; Mon, 26 Sep 2022 08:32:44 +0200 Date: Mon, 26 Sep 2022 08:32:43 +0200 From: Johan Hovold To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v4 1/6] phy: qcom-qmp-pcie: split register tables into common and extra parts Message-ID: References: <20220924160302.285875-1-dmitry.baryshkov@linaro.org> <20220924160302.285875-2-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220924160302.285875-2-dmitry.baryshkov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Sat, Sep 24, 2022 at 07:02:57PM +0300, Dmitry Baryshkov wrote: > SM8250 configuration tables are split into two parts: the common one and > the PHY-specific tables. Make this split more formal. Rather than having > a blind renamed copy of all QMP table fields, add separate struct > qmp_phy_cfg_tables and add two instances of this structure to the struct > qmp_phy_cfg. Later on this will be used to support different PHY modes > (RC vs EP). > > Signed-off-by: Dmitry Baryshkov > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 129 ++++++++++++++--------- > 1 file changed, 77 insertions(+), 52 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > index 7aff3f9940a5..30806816c8b0 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > @@ -1300,31 +1300,30 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = { > QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e), > }; > > -/* struct qmp_phy_cfg - per-PHY initialization config */ > -struct qmp_phy_cfg { > - int lanes; > - > - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ > +struct qmp_phy_cfg_tables { > const struct qmp_phy_init_tbl *serdes_tbl; > int serdes_tbl_num; > - const struct qmp_phy_init_tbl *serdes_tbl_sec; > - int serdes_tbl_num_sec; > const struct qmp_phy_init_tbl *tx_tbl; > int tx_tbl_num; > - const struct qmp_phy_init_tbl *tx_tbl_sec; > - int tx_tbl_num_sec; > const struct qmp_phy_init_tbl *rx_tbl; > int rx_tbl_num; > - const struct qmp_phy_init_tbl *rx_tbl_sec; > - int rx_tbl_num_sec; > const struct qmp_phy_init_tbl *pcs_tbl; > int pcs_tbl_num; > - const struct qmp_phy_init_tbl *pcs_tbl_sec; > - int pcs_tbl_num_sec; > const struct qmp_phy_init_tbl *pcs_misc_tbl; > int pcs_misc_tbl_num; > - const struct qmp_phy_init_tbl *pcs_misc_tbl_sec; > - int pcs_misc_tbl_num_sec; > +}; > + > +/* struct qmp_phy_cfg - per-PHY initialization config */ > +struct qmp_phy_cfg { > + int lanes; > + > + /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ > + struct qmp_phy_cfg_tables common; > + /* > + * Additional init sequence for PHY blocks, providing additional > + * register programming. Unless required it can be left omitted. > + */ > + struct qmp_phy_cfg_tables *extra; > > /* clock ids to be requested */ > const char * const *clk_list; > @@ -1949,31 +1974,31 @@ static int qmp_pcie_power_on(struct phy *phy) > } > > /* Tx, Rx, and PCS configurations */ > - qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1); > - qmp_pcie_configure_lane(tx, cfg->regs, cfg->tx_tbl_sec, cfg->tx_tbl_num_sec, 1); > + qmp_pcie_configure_lane(tx, cfg->regs, cfg->common.tx_tbl, cfg->common.tx_tbl_num, 1); > + qmp_pcie_configure_lane(tx, cfg->regs, cfg->extra->tx_tbl, cfg->extra->tx_tbl_num, 1); Hmm. How did you test this? With your later versions of this series, cfg->extra is generally NULL so this would dereference a NULL pointer. Johan